Embedded gallium-nitride in silicon

Patent metadata

Field	Value
Publication number	US-9685329-B2
Application number	US-201615232865-A
Country	US
Kind code	B2
Filing date	Aug 10, 2016
Priority date	Mar 11, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A method and structure for integrating gallium nitride into a semiconductor substrate. The method may also include means for isolating the gallium nitride from the semiconductor substrate.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, the method comprising:
depositing a first masking layer on a semiconductor substrate;
forming a trench through the first masking layer and into the semiconductor substrate;
forming a gallium-nitride layer in the trench and above the semiconductor substrate and the first masking layer;
forming a second masking layer over a portion of the trench, wherein a covered portion of the gallium nitride layer is located below the second masking layer, and wherein an uncovered portion of the gallium-nitride layer is located at least in the trench;
removing the uncovered portion of the gallium-nitride layer and the second masking layer;
depositing an insulating layer between the covered portion of the gallium-nitride layer and the semiconductor substrate.

2. The method of claim 1 , wherein the semiconductor substrate is a semiconductor on insulator substrate.

3. The method of claim 2 , wherein forming the trench through the first masking layer and into the semiconductor substrate comprises etching through the insulator layer of the semiconductor on insulator substrate.

4. The method of claim 1 , wherein the gallium-nitride layer comprises 30 to 70 mole % gallium and 30 to 70 mole % nitrogen.

5. The method of claim 1 , further comprising forming an aluminum-gallium-nitride layer on the gallium nitride layer.

6. The method of claim 5 , wherein the aluminium-gallium-nitride layer comprises 10 to 50 mole % gallium, 30 to 50 mole % nitrogen, and 10 to 50 mole % aluminum.

7. The method of claim 1 , further comprising forming a semiconductor structure on the semiconductor substrate.

8. The method of claim 7 , wherein the semiconductor structure comprises a structure selected from the group consisting of a fuse, EDRAM, SRAM, and a gate.

9. The method of claim 1 , further comprising forming a GaN structure on the gallium-nitride layer.

10. The method of claim 9 , wherein the GaN structure comprises an LED structure.

11. The method of claim 1 , wherein the semiconductor substrate is a semiconductor on insulator substrate.

12. The method of claim 11 , wherein forming the trench into the semiconductor substrate comprises etching through an insulator layer of the semiconductor on insulator substrate.

13. The method of claim 1 , wherein forming a gallium-nitride layer in the trench and above the semiconductor substrate and the first masking layer comprises epitaxially growing the gallium-nitride layer in the trench and above the semiconductor substrate and the nitride layer.

Assignees

• IBM

Inventors

• Gallagher William J
• Leobandung Effendi
• Sadana Devendra K
• Shahidi Ghavam G

Classifications

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P90/00

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/282

  of inorganic materials · CPC title