Organic light emitting diode pixel compensation circuit, and display panel and display device containing the same

Patent metadata

Field	Value
Publication number	US-9685113-B2
Application number	US-201414536546-A
Country	US
Kind code	B2
Filing date	Nov 7, 2014
Priority date	Jun 23, 2014
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

An OLED pixel compensation circuit includes first, second, third, fourth, fifth, sixth and seventh transistors and a storage capacitor. The first transistor has a gate electrode coupled to a scan signal, a first electrode coupled to a data signal, and a second electrode coupled to a gate electrode of the fifth transistor. The second transistor has a gate electrode coupled to the scan signal, a first electrode coupled to a power supply voltage, and a second electrode coupled to a second electrode of the storage capacitor. The third transistor has a gate electrode coupled to a first light emitting signal, a first electrode coupled to the power supply voltage. The transistors and the storage capacitor are configured to compensate the threshold voltage drift of the fifth transistor, which is the driving transistor for the OLED.

First claim

What is claimed is:

1. An Organic Light Emitting Diode (OLED) pixel compensation circuit, configured to drive an OLED to emit light, the OLED pixel compensation circuit comprising: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a storage capacitor;
a gate electrode of the first transistor is directly electrically connected to a scan signal, a first electrode of the first transistor is directly electrically connected to a data signal, and a second electrode of the first transistor is directly electrically connected to a gate electrode of the fifth transistor;
a gate electrode of the second transistor is directly electrically connected to the scan signal, a first electrode of the second transistor is directly electrically connected to a power supply voltage, and a second electrode of the second transistor is directly electrically connected to a second electrode of the storage capacitor;
a gate electrode of the third transistor is directly electrically connected to a first light emitting signal, a first electrode of the third transistor is directly electrically connected to the power supply voltage, and a second electrode of the third transistor is directly electrically connected to a first electrode of the fifth transistor;
a gate electrode of the fourth transistor is directly electrically connected to the scan signal, a first electrode of the fourth transistor is directly electrically connected to the gate electrode of the fifth transistor, and a second electrode of the fourth transistor is directly electrically connected to the first electrode of the fifth transistor;
a second electrode of the fifth transistor is directly electrically connected to a first electrode of the seventh transistor;
a gate electrode of the sixth transistor is directly electrically connected to the first light emitting signal, a first electrode of the sixth transistor is directly electrically connected to the gate electrode of the fifth transistor, and a second electrode of the sixth transistor is directly electrically connected to the second electrode of the storage capacitor;
a gate electrode of the seventh transistor is directly electrically connected to a second light emitting signal, and a second electrode of the seventh transistor is directly electrically connected to a first electrode of the OLED;
a first electrode of the storage capacitor is directly electrically connected to the first electrode of the seventh transistor; and
a second electrode of the OLED is directly electrically connected to a low-level signal, and the OLED emits light in response to a driving current generated by the fifth transistor.

2. The circuit according to claim 1 , wherein
the first transistor is configured to transfer the data signal to the gate electrode of the fifth transistor under the control of the scan signal;
the second transistor is configured to transfer the power supply voltage to the second electrode of the storage capacitor under the control of the scan signal;
the third transistor is configured to transfer the power supply voltage received by the first electrode of the third transistor to the second electrode of the third transistor under the control of the first light emitting signal;
the fourth transistor is configured to transfer the data signal received by the first electrode of the fourth transistor to the first electrode of the fifth transistor under the control of the scan signal;
the fifth transistor is configured to generate the drive current for driving the OLED to emit light;
the sixth transistor is configured to switch on the first and second electrodes of the sixth transistor under the control of the first light emitting signal;
the seventh transistor is configured to use the drive current generated by the fifth transistor to drive the OLED to emit light; and
the storage capacitor is configured to store a received voltage, and couple a voltage change on the second electrode of the storage capacitor to the first electrode of the storage capacitor or couple a voltage change on the first electrode of the storage capacitor to the second electrode of the storage capacitor.

3. The circuit according to claim 1 , wherein the fifth transistor and the seventh transistor are N-type Metal Oxide Semiconductor (NMOS) transistors.

4. The circuit according to claim 3 , wherein the first transistor, the second transistor and the fourth transistor are NMOS transistors.

5. The circuit according to claim 4 , wherein the third transistor and the sixth transistor are NMOS transistors or P-type Metal Oxide Semiconductor (PMOS) transistors.

6. The circuit according to claim 3 , wherein the first transistor, the second transistor and the fourth transistor are PMOS transistors.

7. The circuit according to claim 6 , wherein the third transistor and the sixth transistor are NMOS transistors or PMOS transistors.

8. The circuit according to claim 5 , wherein, in the case that the third transistor and the sixth transistor are NMOS transistors, the circuit is configured to perform a first stage, a second stage and a third stage, wherein:
in the first stage, the scan signal is a high-level signal, the first light emitting signal is a low-level signal, the second light emitting signal is a high-level signal and the data signal is a high-level signal;
in the second stage, the scan signal comprises a high-level signal, the first light emitting signal is a low-level signal, the second light emitting signal is a low-level signal and the data signal comprises a high-level signal; and
in the third stage, the scan signal is a low-level signal, the first light emitting signal is a high-level signal and the second light emitting signal is a high-level signal.

9. The circuit according to claim 5 , wherein, in the case that the third transistor and the sixth transistor each are PMOS transistors, the circuit is configured to perform a first stage, a second stage and a third stage, wherein:
in the first stage, the scan signal is a high-level signal, the first light emitting signal is a high-level signal, the second light emitting signal is a high-level signal and the data signal is a high-level signal;
in the second stage, the scan signal comprises a high-level signal, the first light emitting signal is a high-level signal, the second light emitting signal is a low-level signal and the data signal comprises a high-level signal; and
in the third stage, the scan signal is a low-level signal, the first light emitting signal is a low-level signal and the second light emitting signal is a high-level signal.

10. The circuit according to claim 7 , wherein, in the case that the third transistor and the sixth transistor each are NMOS transistors, the circuit is configured to perform a first stage, a second stage and a third stage, wherein:
in the first stage, the scan signal is a low-level signal, the first light emitting signal is a low-level signal, the second light emitting signal is a high-level signal and the data signal is a high-level signal;
in the second stage, the scan signal comprises a low-level signal, the first light emitting signal is a low-level signal, the second light emitting signal is a low-level signal and the data signal comprises a high-level signal; and
in the third stage, the scan signal is a high-level signal, the first light emitting signal is a high-level signal and the second light emitting signal is a high-level signal.

11. The circuit according to claim 7 , wherein, in the case that the third transistor and the sixth transistor are PMOS transistors, the circuit is configured to perform a first stage, a second sta

Assignees

• Shanghai Tianma Am-Oled Co Ltd
• Tianma Microelectronics Co Ltd
• Shanghai Tianma Am-Oled Co Ltd

Inventors

• Chen Dan
• Qian Dong

Classifications

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2320/045

  Compensation of drifts in the characteristics of light emitting or modulating elements · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title