Concurrent design process

US9684750B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9684750-B1
Application numberUS-201514837486-A
CountryUS
Kind codeB1
Filing dateAug 27, 2015
Priority dateAug 27, 2015
Publication dateJun 20, 2017
Grant dateJun 20, 2017

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  1. Title

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  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure relates to a method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include receiving, at a client computing device, a user input corresponding to a change to an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may also include implementing the change to the electronic circuit design at the client computing device without receiving authorization from a server computing device and transmitting the implemented change to the electronic circuit design to the server computing device.

First claim

Opening claim text (preview).

What is claimed is: 1. A computer-implemented method for multi-user, at least partially concurrent, electronic circuit design comprising: receiving, at a client computing device, a user input corresponding to a change to an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner; implementing the change to the electronic circuit design at the client computing device without receiving an authorization from a server computing device; transmitting the implemented change to the electronic circuit design to the server computing device; and receiving, from the server computing device, a database identification (“ID”) pool specific to the client computing device. 2. The computer-implemented method of claim 1 , wherein the implementing the change to the electronic circuit design includes updating a version of the electronic circuit design associated with the client computing device. 3. The computer-implemented method of claim 1 , wherein the implementing the change to the electronic circuit design includes updating a display at a graphical user interface associated with the client computing device. 4. The computer-implemented method of claim 1 , further comprising: receiving, from the server computing device, and after the implementing the change, a rejection of the implemented change. 5. The computer-implemented method of claim 1 , further comprising: storing, at the client computing device, a complete version of printed circuit board data associated with the electronic circuit design. 6. The computer-implemented method of claim 1 , wherein the implementing the change to the electronic circuit design at the client computing device and the transmitting the implemented change to the electronic circuit design to the server computing device are at least partially synchronized operations. 7. A non-transitory computer-readable storage medium for a multi-user, at least partially concurrent, electronic circuit design, the non-transitory computer-readable storage medium having stored thereon instructions that when executed by a machine, cause the machine to perform the following operations: receiving, at a client computing device, a user input corresponding to a change to an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner; implementing the change to the electronic circuit design at the client computing device without receiving an authorization from a server computing device; transmitting the implemented change to the electronic circuit design to the server computing device; and receiving, from the server computing device, a database identification (“ID”) pool specific to the client computing device. 8. The non-transitory computer-readable storage medium of claim 7 , wherein the implementing the change to the electronic circuit design includes updating a version of the electronic circuit design associated with the client computing device. 9. The non-transitory computer-readable storage medium of claim 7 , wherein the implementing the change to the electronic circuit design includes updating a display at a graphical user interface associated with the client computing device. 10. The non-transitory computer-readable storage medium of claim 7 , further comprising: receiving, from the server computing device, and after the implementing the change, a rejection of the implemented change. 11. The non-transitory computer-readable storage medium of claim 7 , further comprising: storing, at the client computing device, a complete version of printed circuit board data associated with the electronic circuit design. 12. The non-transitory computer-readable storage medium of claim 7 , wherein the implementing the change to the electronic circuit design at the client computing device and the transmitting the implemented change to the electronic circuit design to the server computing device are at least partially synchronized operations. 13. A system for multi-user, at least partially concurrent, electronic circuit design comprising: a client computing device configured to perform an action to receive a user input corresponding to a change to an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner, the client computing device including at least one processor configured to implement the change to the electronic circuit design at the client computing device without receiving an authorization from a server computing device, the at least one processor further configured to perform an action to transmit the implemented change to the electronic circuit design to the server computing device, the at least one processor configured to receive, from the server computing device, a database identification (“ID”) pool specific to the client computing device. 14. The system of claim 13 , wherein implementing the change to the electronic circuit design includes updating a version of the electronic circuit design associated with the client computing device. 15. The system of claim 13 , wherein implementing the change to the electronic circuit design includes updating a display at a graphical user interface associated with the client computing device. 16. The system of claim 13 , the at least one processor further configured to perform: receiving, from the server computing device, and after implementation of the change, a rejection of the implemented change. 17. The system of claim 13 , the at least one processor further configured to perform: storing, at the client computing device, a complete version of printed circuit board data associated with the electronic circuit design.

Assignees

Inventors

Classifications

  • G06F30/30Primary

    Circuit design · CPC title

  • CAD in a network environment, e.g. collaborative CAD or distributed simulation · CPC title

  • Physics · mapped topic

  • Physics · mapped topic

Patent family

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External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9684750B1 cover?
The present disclosure relates to a method for multi-user, at least partially concurrent, electronic circuit design. Embodiments may include receiving, at a client computing device, a user input corresponding to a change to an electronic circuit design, wherein the electronic circuit design is accessible by multiple users in an at least partially concurrent manner. Embodiments may also include …
Who is the assignee on this patent?
Cadence Design Systems Inc
What technology area does this patent fall under?
Primary CPC classification G06F30/30. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 20 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).