Peripheral component interconnect express (PCIe) ping in a switch-based environment

Patent metadata

Field	Value
Publication number	US-9684618-B2
Application number	US-201414251325-A
Country	US
Kind code	B2
Filing date	Apr 11, 2014
Priority date	Mar 6, 2014
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A sideband PCI Express (PCIe) packet initiator in a distributed PCIe switch fabric verifies a PCIe connection between a host device and a PCIe endpoint device without having to power on the host device. The packet initiator assembles a PCIe test packet that acts as a ping for testing reachability of the endpoint device, from the perspective of the host device. The test packet may also verify configurations and settings of the path to the endpoint device. The distributed switch fabric is configured to compare completion data with expected results to verify the PCIe connection, without having to boot the host device.

First claim

What is claimed is:

1. A method to verify connections of a distributed switch comprising a plurality of switch modules, each switch module of the plurality having at least one port for establishing connections according to a predefined interface, the method comprising:
receiving an indication to verify a connection from a host device to an endpoint device, wherein the host device is connected to an upstream port of a first switch module of the plurality of switch modules, and the endpoint device is connected to a downstream port of the distributed switch;
transmitting a test packet from the upstream port of the first switch module to the downstream port of the distributed switch without powering on the host device, wherein transmitting the test packet comprises generating, by operation of a computer processor of the distributed switch, the test packet which includes a first data field identifying the upstream port of the first switch module as a source and a second data field identifying the endpoint device as a destination;
receiving a response packet from the downstream port, wherein the response packet comprises completion data resulting from processing the test packet; and
responsive to determining the completion data matches one or more values expected to be received in response to the test packet, determining the connection has been established between the host device connected to the upstream port and the endpoint device connected to the downstream port of the distributed switch.

2. The method of claim 1 , wherein the first data field is a requester identifier associated with the upstream port and the second data field is a completer identifier associated with the endpoint device.

3. The method of claim 1 , wherein the test packet is generated by a packet initiator module not directly connected to a physical interface of the host device.

4. The method of claim 1 , further comprising:
responsive to determining the completion data does not match the one or more expected values, generating an error associated with the connection between the host device and the endpoint device.

5. The method of claim 1 , further comprising:
responsive to determining the response packet comprises a requester identifier associated with the upstream port, storing the completion data of the response packet in a memory register of the first switch module.

6. The method of claim 1 , wherein determining whether the completion data matches the one or more expected values comprises:
modifying the completion data based on a mask value associated with the test packet; and
comparing the modified completion data with the one or more expected values.

7. The method of claim 1 , wherein the predefined interface is a Peripheral Component Interconnect Express (PCIe) interface, and wherein the test packet includes a PCIe configuration transaction for the endpoint device.

Assignees

• IBM

Inventors

• Mcglone Elizabeth A
• Vanderpool Brian T
• Williams Jeffrey B
• Wollbrink Curtis C

Classifications

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F1/3278

  Power saving in modem or I/O interface · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title