Translation lookaside buffer for guest physical addresses in a virtual machine

Patent metadata

Field	Value
Publication number	US-9684605-B2
Application number	US-201514628405-A
Country	US
Kind code	B2
Filing date	Feb 23, 2015
Priority date	Feb 23, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

Embodiments of an invention for a guest-physical address translation lookaside buffer are disclosed. In an embodiment, a processor includes an instruction decoder, a control register, and memory address translation hardware. The instruction decoder is to receive an instruction to transfer control of the processor to guest software to execute on a virtual machine. The virtual machine is to have a plurality of resources to be controlled by a virtual machine monitor. The virtual machine monitor is to execute on a host machine having a host-physical memory to be accessed using a plurality of host-physical addresses. The plurality of resources is to include a guest-physical memory. The guest software is to access the guest-physical memory using a plurality of guest-virtual addresses. The control register is to store a pointer to a plurality of virtual address page tables. The memory address translation hardware is to translate, without causing a virtual machine exit, guest-virtual addresses to host-physical addresses using the plurality of virtual address page tables and a plurality of extended page tables. The memory address translation hardware includes a virtual address translation lookaside buffer in which to store a plurality of virtual address entries corresponding to guest-virtual address to host-physical address translations. The memory address translation hardware also includes a guest-physical address translation lookaside buffer in which to store a plurality of guest-physical address entries corresponding to guest-physical address to host-physical address translations.

First claim

What is claimed is:

1. A processor comprising:
an instruction decoder to receive an instruction to transfer control of the processor to guest software to execute on a virtual machine, the virtual machine to have a plurality of resources to be controlled by a virtual machine monitor to execute on a host machine having a host-physical memory to be accessed using a plurality of host-physical addresses, the plurality of resources to include a guest-physical memory, the guest software to access the guest-physical memory using a plurality of guest-virtual addresses;
a control register to store a pointer to a plurality of virtual address page tables;
memory address translation hardware to translate, without causing a virtual machine exit, guest-virtual addresses to host-physical addresses using the plurality of virtual address page tables to translate guest-virtual addresses to guest-physical addresses and a plurality of extended page tables to translate guest-physical addresses to host-physical addresses, the memory address translation hardware including
first circuitry to combine a first portion of a guest-virtual address with the pointer to the plurality of virtual address page tables to calculate a first guest-physical address,
second circuitry to combine a first portion of the first guest-physical address with one of a plurality of extended page table pointers to calculate a first host-physical address of a first entry in a first extended page table in a first level of hierarchy,
a virtual address translation lookaside buffer in which to store a plurality of virtual address entries corresponding to guest-virtual address to host-physical address translations, and
a guest-physical address translation lookaside buffer in which to store a plurality of guest-physical address entries corresponding to guest-physical address to host-physical address translations, each of the plurality of guest-physical address entries including a field in which to store one of the plurality of extended page table pointers to indicate whether the entry is valid for an active set of extended page tables.

2. The processor of claim 1 , wherein the plurality of virtual address page tables includes four levels of hierarchy.

3. The processor of claim 2 , wherein the plurality of extended page tables includes four levels of hierarchy.

4. The processor of claim 3 , wherein the memory address translation hardware also includes third circuitry to combine a second portion of the first guest-physical address with a first base address from the first entry to calculate a second host-physical address of a second entry in a second extended page table in a second level of hierarchy.

5. The processor of claim 4 , wherein the memory address translation hardware also includes fourth circuitry to combine a third portion of the first guest-physical address with a second base address from the second entry to calculate a third host-physical address of a third entry in a third extended page table in a third level of hierarchy.

6. The processor of claim 5 , wherein the memory address translation hardware also includes fifth circuitry to combine a fourth portion of the first guest-physical address with a third base address from the third entry to calculate a fourth host-physical address of a fourth entry in a fourth extended page table in a fourth level of hierarchy.

7. The processor of claim 6 , wherein the memory address translation hardware also includes sixth circuitry to combine a fifth portion of the first guest-physical address with a fourth base address from the fourth entry to calculate a fifth host-physical address.

8. The processor of claim 7 , wherein the fourth base address is a base address of a page in host-physical memory.

9. The processor of claim 8 , wherein, in response to a page walk from the first guest-physical address to the base address of the page in host-physical memory, a guest-physical address entry is stored in the guest-physical address translation lookaside buffer.

10. The processor of claim 9 , wherein the guest-physical address entry in the guest-physical address translation lookaside buffer is to include the first portion of the first guest-physical address, the second portion of the guest-physical address, the third portion of the guest-physical address, and the fourth portion of the guest-physical address in a guest-physical address index to the guest-physical address translation lookaside buffer.

11. The processor of claim 10 , wherein the guest-physical address entry in the guest-physical address translation lookaside buffer is also to include the base address of the page in host-physical memory.

12. The processor of claim 11 , wherein the guest-physical address entry in the guest-physical address translation lookaside buffer is also to include cumulative access permission information associated with the base address of the page in host-physical memory.

13. The processor of claim 12 , wherein the cumulative access permission information is based on a first access permission from the first extended page table, a second access permission from the second extended page table, a third access permission from the third extended page table, and a fourth access permission from the fourth extended page table.

14. The processor of claim 13 , wherein the memory address translation hardware is to use the guest-physical address entry, instead of the plurality of extended page tables, to translate the guest-physical address index to the base address of the page in host-physical memory.

15. A method comprising:
transferring control of a processor to guest software to execute on a virtual machine, the virtual machine to have a plurality of resources to be controlled by a virtual machine monitor executing on a host machine having a host-physical memory to be accessed using a plurality of host-physical addresses, the plurality of resources to include a guest-physical memory, the guest software to access the guest-physical memory using a plurality of guest-virtual addresses;
performing, by processor hardware without exiting the virtual machine, an initial translation of a guest-virtual address to a host-physical address, including a page walk through a plurality of virtual address page tables and a plurality of extended page tables;
storing, by processor hardware in response to the page walk without exiting the virtual machine, an entry in a guest-physical address translation lookaside buffer, the entry including a portion of a guest-physical address, a portion of the host-physical address, and one of a plurality of extended page table pointers to indicate whether the entry is valid for an active set of extended page tables; and
performing, by processor hardware without exiting the virtual machine, a subsequent translation of the guest-virtual address to the host-physical address, using the entry in the guest-physical address translation lookaside buffer to translate the portion of the guest-physical address to the portion of the host-physical address instead of performing a portion of the page walk.

16. A system comprising:
a host-physical memory to be accessed using a plurality of host-physical addresses; and
a processor including:
an instruction decoder to receive an instruction to transfer control of the processor to guest software to execute on a virtual machine, the virtual machine to have a plurality of resources to be controlled by a virtual machine monitor, the plurality of resources to include a guest-physical memory, the guest software to access the guest-physical memory using a plurality of guest-virtual addresses;
a cont

Assignees

• Intel Corp

Inventors

• Shanbhogue Vedvyas
• Bryant Christopher

Classifications

• G06F12/1036 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title