System test compliance tool

Patent metadata

Field	Value
Publication number	US-9684586-B2
Application number	US-201514884180-A
Country	US
Kind code	B2
Filing date	Oct 15, 2015
Priority date	Oct 15, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

An apparatus includes a memory and a processor. The memory stores a test plan, a plurality of performed steps, a configuration for a test environment in which the test was performed, and a result of the test. The processor compares the plurality of performed steps to the plurality of planned steps, compares the configuration for a first test environment and the configuration for the second test environment, and determines whether an action of the plurality of actions resulted in a failure. The processor presents a first chart, a second chart, and a third chart the results of the comparisons and determination. The processor deploys an application corresponding to the test plan if each step of the plurality of planned steps was performed during the test, if the second test environment was configured according to the configuration for the first test environment, and if the failure was fixed.

First claim

What is claimed is:

1. An apparatus comprising:
a memory configured to store:
a plurality of steps performed during a test;
a configuration for a first test environment in which the test was performed;
a result of the test; and
a test plan comprising:
a plurality of planned steps to be performed during the test; and
a configuration for a second test environment; and

a processor communicatively coupled to the memory, the processor configured to:
compare the plurality of steps performed during the test to the plurality of planned steps to determine that a step of the plurality of planned steps was not performed during the test;
present, on a display, a first chart that indicates each step of the plurality of planned steps and that the determined step of the plurality of planned steps was not performed during the test;
compare the configuration for the first test environment and the configuration for the second test environment to determine whether the first test environment was configured according to the configuration for the second test environment;
present, on the display, a second chart that indicates whether the first test environment was configured according to the configuration for the second test environment;
determine, based on the result of the test, that the test resulted in a failure;
present, on the display, a third chart that indicates the failure; and
deploy an application corresponding to the test plan if each step of the plurality of planned steps was performed during the test, if the first test environment was configured according to the configuration for the second test environment, and if the failure was fixed.

2. The apparatus of claim 1 , wherein the configuration for the second test environment specifies at least one of an operating system, a patch level, and a hardware specification.

3. The apparatus of claim 1 , wherein the processor is further configured to present, on the display, a fourth chart that indicates:
a plurality of tests; and
whether each test of the plurality of tests corresponds to an existing test plan.

4. The apparatus of claim 1 , wherein:
the memory is further configured to store a step that is not included in the test plan; and
the processor is further configured to:
determine whether the step that is not included in the test plan should be included in the test plan; and
present, on the display, a fourth chart that indicates the step that is not included in the test plan if the step that is not included in the test plan should be included in the test plan.

5. The apparatus of claim 1 , wherein:
the test verifies whether the application is compliant; and
the application is deployed in response to a determination that the each step of the plurality of planned steps was performed during the test and that the first test environment was configured according to the configuration for the second test environment.

6. The apparatus of claim 1 , wherein the processor is further configured to determine whether the failure has been repaired.

7. The apparatus of claim 1 , wherein one or more of the first chart, the second chart, and the third chart further identifies a tester who performed the test.

8. A method comprising:
storing, by a memory, a plurality of steps performed during a test;
storing, by the memory, a configuration for a first test environment in which the test was performed;
storing, by the memory, a result of the test;
storing, by the memory, a test plan comprising:
a plurality of planned steps to be performed during the test; and
a configuration for a second test environment;

comparing, by a processor communicatively coupled to the memory, the plurality of steps performed during the test to the plurality of planned steps to determine that a step of the plurality of planned steps was not performed during the test;
presenting, on a display, a first chart that indicates each step of the plurality of planned steps and that the determined step of the plurality of planned steps was not performed during the test;
comparing, by the processor, the configuration for the first test environment and the configuration for the second test environment to determine whether the first test environment was configured according to the configuration for the second test environment;
presenting, on the display, a second chart that indicates whether the first test environment was configured according to the configuration for the second test environment;
determining, by the processor, based on the result of the test, that the test resulted in a failure;
presenting, on the display, a third chart that indicates the failure; and
deploying, by the processor, an application corresponding to the test plan if each step of the plurality of planned steps was performed during the test, if the first test environment was configured according to the configuration for the second test environment, and if the failure was fixed.

9. The method of claim 8 , wherein the configuration for the second test environment specifies at least one of an operating method, a patch level, and a hardware specification.

10. The method of claim 8 , further comprising presenting, on the display, a fourth chart that indicates:
a plurality of tests; and
whether each test of the plurality of tests corresponds to an existing test plan.

11. The method of claim 8 , further comprising:
storing, by the memory, a step that is not included in the test plan;
determining, by the processor, whether the step that is not included in the test plan should be included in the test plan; and
presenting, on the display, a fourth chart that indicates the step that is not included in the test plan if the step that is not included in the test plan should be included in the test plan.

12. The method of claim 8 , wherein:
the test verifies whether the application is compliant; and
the application is deployed in response to a determination that the each step of the plurality of planned steps was performed during the test and that the first test environment was configured according to the configuration for the second test environment.

13. The method of claim 8 , further comprising determining, by the processor, whether the failure has been repaired.

14. The method of claim 8 , wherein one or more of the first chart, the second chart, and the third chart further identifies a tester who performed the test.

15. A system comprising:
a compliance management server comprising a memory configured to:
store a plurality of steps performed during a test;
store a configuration for a first test environment in which the test was performed;
store a result of the test; and
store a test plan comprising:
a plurality of planned steps to be performed during the test; and
a configuration for a second test environment; and

a compliance management device communicatively coupled to the compliance management server, the compliance management device comprising a processor configured to:
compare the plurality of steps performed during the test to the plurality of planned steps to determine that a step of the plurality of planned steps was not performed during the test;
present, on a display, a first chart that indicates each step of the plurality of planned steps and that the determined step of the plurality of planned steps was not performed during the test;
compare the configuration for the first test environment and the configuration for the second test environment to determine whether the first test environment was configured according to the configuration for the second test environment;
pres

Assignees

• Bank Of America

Inventors

• Anand Mandeep Singh
• Kumar Sushil
• Kumar Hitendra

Classifications

• G06F11/3676 Primary

  for coverage analysis · CPC title

• G06F8/60

  Software deployment · CPC title

• G06F11/3688 Primary

  for test execution, e.g. scheduling of test suites · CPC title

• G06F8/00

  Arrangements for software engineering (testing or debugging G06F11/36; administrative, planning or organisation aspects of software project management G06Q10/06) · CPC title