Code generation method and information processing apparatus
US-9213548-B2 · Dec 15, 2015 · US
US9684514B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9684514-B2 |
| Application number | US-201414482042-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 10, 2014 |
| Priority date | Sep 10, 2014 |
| Publication date | Jun 20, 2017 |
| Grant date | Jun 20, 2017 |
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Official abstract text for this publication.
A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.
Opening claim text (preview).
What is claimed is: 1. A system for generating a condition code that depends upon a numerical output of a floating point operation for a processing pipeline, the system comprising: logic circuitry configured to determine a classification for the floating point operation of a received instruction, wherein the determine the classification is by determining that the floating point operation of the received instruction is a convert to integer operation for an operand; calculate, in response to the classification and using condition determination logic, a value for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available, wherein the calculate the condition code is by determining that the operand is a valid, non-zero, number and by detecting that the convert to integer operation will not result in an overflow condition by detecting that an exponent and alignment of the operand are outside of a range of values; and provide the value for the condition code to branch decision logic of the processing pipeline. 2. The system of claim 1 , wherein the logic circuitry is configured to detect that the convert to integer operation will not result in an overflow condition by detecting that an exponent and alignment of the operand are within a first range of values, and in response, by detecting that a mantissa of the operand is within of a second range of values and by checking bits shifted out of a useable, integer portion of the mantissa.
Condition code generation, e.g. Carry, Zero flag · CPC title
to perform conditional operations, e.g. using predicates or guards · CPC title
with variable precision · CPC title
Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion · CPC title
Pipeline control instructions, e.g. multicycle NOP · CPC title
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