Calibration scheme for improving flexibility on platform implementation

Patent metadata

Field	Value
Publication number	US-9684350-B2
Application number	US-201514671127-A
Country	US
Kind code	B2
Filing date	Mar 27, 2015
Priority date	Mar 27, 2015
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

An apparatus is described herein. The apparatus includes a plurality of electrical components, wherein at least one component is to increase a total impedance at a port. The apparatus also includes a comparator, wherein the comparator is to determine an additional impedance from the plurality of electrical components at the port and adjust the impedance to maintain signal integrity along a trace to the port in response to a device being coupled with the port.

First claim

What is claimed is:

1. An apparatus, comprising:
a high speed pull-up driver having a variable output impedance, wherein the high speed pull-up driver provides a voltage source of one volt;
a comparator coupled to the high speed pull-up driver to compare an output voltage of the high speed pull-up driver to a reference voltage, and to signal a result of the comparison to a finite state machine, the finite state machine to select the reference voltage for the comparison and to control the output impedance of the high speed pull-up driver based on the result of the comparison and the selected reference voltage, wherein the reference voltage and the voltage source of the high speed pull-up driver are inputs to the comparator.

2. The apparatus of claim 1 , comprising an additional impedance from a plurality of electrical components, wherein the output impedance is controlled based on the additional impedance.

3. The apparatus of claim 1 , wherein the output impedance is controlled to be approximately 45 ohms.

4. The apparatus of claim 1 , wherein detection of the output impedance occurs when a driver termination exists.

5. The apparatus of claim 1 , wherein the reference voltage is to correspond to a platform resistance value.

6. The apparatus of claim 1 , wherein the reference voltage is mapped to a platform resistance value via a look up table.

7. The apparatus of claim 1 , wherein the reference voltage is mapped to a platform resistance value via a look up table and the look up table comprises a corresponding resistance compensation value.

8. The apparatus of claim 1 , wherein the output impedance is adjusted to ensure high quality data transmission.

9. The apparatus of claim 1 , wherein the reference voltage is to adjust a receiver voltage of a device.

10. A system, comprising:
a device, wherein the device is to couple with a host, and in response to the device being coupled with the host, a platform resistance detection is performed where a reference voltage that is to drive an output of a comparator high is mapped to a corresponding resistance compensation value to be applied to a pull up resistance of the host, wherein the reference voltage and a high speed pull-up driver voltage source are inputs to the comparator.

11. The system of claim 10 , wherein a finite state machine is to determine the reference voltage that is to drive an output of a comparator high via a reference voltage table.

12. The system of claim 10 , wherein the platform resistance is a resistance as measured at a connector of the device during a chirp event.

13. The system of claim 10 , wherein the platform resistance is adjusted to be approximately 45 ohms.

14. The system of claim 10 , wherein detection of the resistance occurs when a driver termination exists.

15. The system of claim 10 , wherein the platform resistance is adjusted based on the reference voltage and a look up table for platform resistance compensation.

16. The system of claim 10 , wherein a look up table is computed using a voltage divider concept.

17. The system of claim 10 , wherein platform resistance detection and adjustment is to occur during a device Chirp-K period immediately following a first host reset.

18. The system of claim 10 , wherein resistance is adjusted to ensure a corresponding eye diagram is clear.

Assignees

• Intel Corp

Inventors

• Low Chia How

Classifications

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F1/3253

  Power saving in bus · CPC title

• G06F1/263 Primary

  Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3278

  Power saving in modem or I/O interface · CPC title