Liquid crystal display device

Patent metadata

Field	Value
Publication number	US-9684215-B2
Application number	US-201615140577-A
Country	US
Kind code	B2
Filing date	Apr 28, 2016
Priority date	Aug 31, 2006
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.

First claim

What is claimed is:

1. A display device comprising:
a pixel region provided over a first substrate; and
a scan line driver circuit provided over the first substrate,
wherein the scan line driver circuit includes
a first transistor, a second transistor, a third transistor, and a fourth transistor,
wherein the first, second, third, and fourth transistors are the same polarity,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, the other of the source and the drain of the first transistor is electrically connected to a first wiring to which at least a first clock signal is input, and a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring to which at least a first potential is input, and a gate of the second transistor is electrically connected to a gate of the fourth transistor,
wherein the one of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the first wiring has a first region and the second wiring has a second region, and
wherein a width of the first region of the first wiring is larger than a width of the second region of the second wiring.

2. A display module including:
the display device according to claim 1 ; and
a flexible printed circuit.

3. An electronic device including:
the display module according to claim 2 ; and
at least one of an operation switch, a battery, an antenna, and a housing.

4. A display device comprising:
a pixel region provided over a first substrate; and
a scan line driver circuit provided over the first substrate,
wherein the scan line driver circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor,
wherein the first, second, third, and fourth transistors are the same polarity,
wherein a channel width of the first transistor is larger than a channel width of each of the second transistor, the third transistor, and the fourth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, the other of the source and the drain of the first transistor is electrically connected to a first wiring to which at least a first clock signal is input, and a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring to which at least a first potential is input, and a gate of the second transistor is electrically connected to a gate of the fourth transistor,
wherein the one of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein the first wiring has a first region and the second wiring has a second region, and
wherein a width of the first region of the first wiring is larger than a width of the second region of the second wiring.

5. A display module including:
the display device according to claim 4 ; and
a flexible printed circuit.

6. An electronic device including:
the display module according to claim 5 ; and
at least one of an operation switch, a battery, an antenna, and a housing.

7. A display device comprising:
a pixel region provided over a first substrate; and
a scan line driver circuit provided over the first substrate,
wherein the scan line driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
wherein the first, second, third, fourth, and fifth transistors are the same polarity,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the fifth transistor, the other of the source and the drain of the first transistor is electrically connected to a first wiring to which at least a first clock signal is input, and a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring to which at least a first potential is input, and a gate of the second transistor is electrically connected to a gate of the fourth transistor,
wherein the one of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein a gate of the fifth transistor is electrically connected to a third wiring to which at least a second clock signal is input,
wherein the first wiring has a first region, the second wiring has a second region, and the third wiring has a third region,
wherein a width of the first region of the first wiring is larger than a width of the second region of the second wiring, and
wherein a width of the third region of the third wiring is larger than the width of the second region of the second wiring.

8. A display module including:
the display device according to claim 7 ; and
a flexible printed circuit.

9. An electronic device including:
the display module according to claim 8 ; and
at least one of an operation switch, a battery, an antenna, and a housing.

10. A display device comprising:
a pixel region provided over a first substrate; and
a scan line driver circuit provided over the first substrate,
wherein the scan line driver circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
wherein the first, second, third, fourth, and fifth transistors are the same polarity,
wherein a channel width of the first transistor is larger than a channel width of each of the second transistor, the third transistor, and the fourth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the fifth transistor, the other of the source and the drain of the first transistor is electrically connected to a first wiring to which at least a first clock signal is input, and a gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring to which at least a first potential is input, and a gate of the second transistor is electrically connected to a gate of the fourth transistor,
wherein the one of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,
wherein a gate of the fifth transistor is electrically connected to a third wiring to which at least a second clock signal is input,
wherein the first wiring has a first region, the second wiring has a second region, and the third wiring has a third region,
wherein a width of the first region of the first wiring is larger than a width of the second region of the second wiring, and
wherein a width of the third region of the third wiring is larger than the width of the second region of the second wiring.

11. A display module including:
the display device according to claim 10 ; and
a flexible printed circuit.

12. An electronic device including:
the display module

Assignees

• Semiconductor Energy Lab

Inventors

• Umezaki Atsushi

Classifications

• H10P72/0454

  surrounding a central transfer chamber · CPC title

• G09G3/342 Primary

  using several illumination sources separately controlled corresponding to different display panel areas, e.g. along one dimension such as lines · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G02F1/13306

  Circuit arrangements or driving methods for the control of single liquid crystal cells (G02F1/132, G02F1/133382 take precedence) · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title