Integrated ultra wideband transceiver

Patent metadata

Field	Value
Publication number	US-9681389-B2
Application number	US-201414768143-A
Country	US
Kind code	B2
Filing date	Feb 17, 2014
Priority date	Feb 15, 2013
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

An integrated ultra wideband transceiver. The transceiver comprises a transmitter, a receiver, and at least one on-chip monopole antenna electrically connected to at least one of the transmitter or receiver for transmitting and/or receiving electrical signals. The transceiver further comprises a clock generator comprising a temperature-compensated relaxation oscillator, a baseband controller electrically connected to, and configured to exert a measure of control over, at least one the transmitter, receiver, or clock generator, and a micro-battery operative to provide operating power to each of the transmitter, receiver, clock generator, and baseband controller.

First claim

The invention claimed is:

1. An integrated ultra wideband transceiver, comprising:
a transmitter;
a receiver;
a clock generator;
a baseband controller electrically connected to, and configured to exert a measure of control over, at least one of the transmitter, receiver, or clock generator; and
a micro-battery operative to provide operating power to each of the transmitter, receiver, clock generator, and baseband controller,
wherein the baseband controller is configured to control a duty cycle of the receiver at a frequency that is faster than a bit rate at which the receiver receives data, and such that the receiver is in an active state of operation for only a portion of each bit cycle corresponding to the bit rate, and further wherein the portion of each bit cycle that the receiver is active is less than the entirety of the bit cycle.

2. The transceiver of claim 1 , further comprising at least one monopole antenna electrically connected to at least one of the transmitter or receiver for transmitting and/or receiving electrical signals.

3. The transceiver of claim 2 , wherein the at least one monopole antenna comprises at least one on-chip monopole antenna.

4. The transceiver of claim 2 , wherein the transmitter and receiver are configured to be electrically connected to at least off-chip monopole antenna.

5. The transceiver of claim 1 , wherein the clock generator comprises a temperature-compensated relaxation oscillator.

6. The transceiver of claim 1 , further comprising a current limiter electrically connected between the micro-battery and at least one of the transmitter, receiver, clock generator, or baseband controller.

7. The transceiver of claim 6 , further comprising a storage capacitor electrically connected to the current limiter and the at least one of the transmitter, receiver, clock generator, or baseband controller.

8. The transceiver of claim 7 , wherein the storage capacitor comprises an on-chip storage capacitor.

9. The transceiver of claim 1 , wherein at least one of the transmitter, receiver, clock generator, or baseband controller is configured to operate in a sleep state, and may be toggled back and forth between an active state and the sleep state.

10. The transceiver of claim 9 , wherein the baseband controller is operable to control the duty cycle of at least one of the transmitter, receiver, or clock generator to cause the at least one of the transmitter, receiver, or clock generator to enter the sleep state.

11. The transceiver of claim 1 , wherein the clock generator comprises a relaxation oscillator.

12. The transceiver of claim 11 , wherein the relaxation oscillator of the clock generator comprises an RC network connected in circuit with a hysteretic comparator.

13. The transceiver of claim 12 , wherein the RC network comprises a first resistor electrically connected in circuit with a first capacitor, and a second resistor electrically connected in circuit with a second capacitor, wherein the combination of the first resistor and the first capacitor is electrically connected in circuit with the combination of the second resistor and the second capacitor.

14. The transceiver of claim 12 , wherein when an output of the comparator is a logic high, a capacitor of the RC network is charged until the voltage of the capacitor exceeds a first predetermined threshold, then the output of the comparator goes to a logic low and the capacitor is discharged until the voltage of the capacitor reaches a second predetermined threshold.

15. The transceiver of claim 1 , wherein the transmitter comprises a combination power amplifier and voltage controlled oscillator, and a pulse generator.

16. The transceiver of claim 1 , wherein the receiver comprises at least one RF gain stage configured to amplify pulses received by the receiver, and a squaring mixer configured to down-convert the pulses amplified by the at least one RF gain stage.

17. The transceiver of claim 16 , wherein the receiver further comprises a comparator disposed downstream of the squaring mixer and configured to digitize pulses received thereby.

18. The transceiver of claim 1 , wherein the receiver comprises a plurality of RF gain stages, and further wherein the RF gain stages are stacked.

19. The transceiver of claim 1 , wherein the power drawn by the receiver when in an active state of operation is greater than a peak power of the micro-battery.

20. An integrated ultra wideband transceiver, comprising:
a transmitter;
a receiver;
at least one on-chip monopole antenna electrically connected to at least one of the transmitter or receiver for transmitting and/or receiving electrical signals;
a clock generator;
a baseband controller electrically connected to, and configured to exert a measure of control over, at least one of the transmitter, receiver, or clock generator; and
a micro-battery operative to provide operating power to each of the transmitter, receiver, clock generator, and baseband controller,
wherein the baseband controller is configured to control a duty cycle of the receiver at a frequency that is faster than a bit rate at which the receiver receives data, and such that the receiver is in an active state of operation for only a portion of each bit cycle corresponding to the bit rate, and further wherein the portion of each bit cycle that the receiver is active is less than the entirety of the bit cycle.

21. The transceiver of claim 20 , further comprising a current limiter electrically connected between the micro-battery and at least one of the transmitter, receiver, clock generator, or baseband controller.

22. The transceiver of claim 21 , further comprising an on-chip storage capacitor electrically connected to the current limiter and the at least one of the transmitter, receiver, clock generator, or baseband controller.

23. The transceiver of claim 20 , wherein the at least one on-chip antenna comprises a first on-chip monopole antenna electrically connected to the transmitter for transmitting electrical signals, and a second on-chip monopole antenna electrically connected to the receiver for receiving electrical signals.

24. An integrated ultra wideband transceiver, comprising:
a transmitter;
a receiver;
a first on-chip monopole antenna electrically connected to the transmitter for transmitting electrical signals, and a second on-chip monopole antenna electrically connected to the receiver for receiving electrical signals;
a clock generator;
a baseband controller electrically connected to, and configured to exert a measure of control over, at least one of the transmitter, receiver, or clock generator;
a micro-battery operative to provide operating power to each of the transmitter, receiver, clock generator, and baseband controller;
a current limiter electrically connected between the micro-battery and at least one of the transmitter, receiver, clock generator, or baseband controller; and
an on-chip storage capacitor electrically connected to the current limiter and the at least one of the transmitter, receiver, clock generator, or baseband controller,
wherein the baseband controller is configured to control a duty cycle of the receiver at a frequency that is faster than a bit rate at which the receiver receives data, and such that the receiver is in an active state of operation for only a portion of each bit cycle corresponding to the bit rate, and further wherein the portion of each bit cycle that the receiver is active is l

Assignees

• Univ Michigan Regents

Inventors

• Wentzloff David D
• Brown Jonathan K
• Huang Kuo-Ken
• Ansari Elnaz
• Rogel Ryan R

Classifications

• H04W52/029 Primary

  reducing the clock frequency of the controller · CPC title

• H03K3/0231

  Astable circuits {(H03K3/0315 takes precedence)} · CPC title

• H04B1/40

  Circuits · CPC title

• H04B1/71637

  Receiver aspects (H04B1/7183 takes precedence) · CPC title

• H04B1/7183

  Synchronisation · CPC title