Apparatus for compensation of electronic circuitry and associated methods

Patent metadata

Field	Value
Publication number	US-9680420-B2
Application number	US-201514869924-A
Country	US
Kind code	B2
Filing date	Sep 29, 2015
Priority date	Sep 29, 2015
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

An apparatus includes a multi-stage amplifier. The multi-stage amplifier includes first, second, and third amplifier circuits coupled in a cascade configuration. The multi-stage amplifier further includes first, second, and third compensation networks. The first compensation network is coupled between the output of the third amplifier circuit and the input of the second amplifier circuit. The second compensation network is coupled between the output of the third amplifier circuit and the input of the third amplifier circuit. The third compensation network is coupled between the output of the second amplifier circuit and the input of the second amplifier circuit.

First claim

The invention claimed is:

1. An apparatus comprising:
a multi-stage amplifier comprising:
first, second, and third amplifier circuits coupled in a cascade configuration;
a bias voltage source coupled to an inverting input of the second amplifier circuit via a resistor to provide a DC operating point for the second amplifier circuit; and
first, second, and third compensation networks, wherein the first compensation network is coupled between the output of the third amplifier circuit and a non-inverting input of the second amplifier circuit, the second compensation network is coupled between the output of the third amplifier circuit and the input of the third amplifier circuit, and the third compensation network is coupled between the output of the second amplifier circuit and the inverting input of the second amplifier circuit.

2. The apparatus according to claim 1 , wherein the first amplifier circuit is DC coupled to the second amplifier circuit.

3. The apparatus according to claim 2 , wherein the second amplifier circuit is DC coupled to the third amplifier circuit.

4. The apparatus according to claim 1 , wherein the third compensation network comprises a first capacitor.

5. The apparatus according to claim 4 , wherein the first capacitor removes a right-hand-zero of a transfer function of the multi-stage amplifier.

6. The apparatus according to claim 4 , wherein the first capacitor reduces a noise level of the multi-stage amplifier.

7. The apparatus according to claim 4 , wherein the first capacitor improves a gain margin of the multi-stage amplifier.

8. The apparatus according to claim 4 , wherein the second compensation network comprises a second capacitor.

9. The apparatus according to claim 8 , wherein the first compensation network comprises a third capacitor.

10. The apparatus according to claim 9 , comprising an integrated circuit (IC), wherein the multi-stage amplifier is integrated in the IC.

11. A multi-stage amplifier comprising:
a first amplifier circuit having first and second inputs and an output, the first amplifier circuit coupled to receive an input signal of the compensated multi-stage amplifier at the first input of the first amplifier circuit;
a second amplifier circuit having first and second inputs and an output, the first input of the second amplifier circuit coupled to the output of the first amplifier circuit;
a third amplifier circuit having an input and an output, the input of the third amplifier circuit coupled to the output of the second amplifier circuit, the output of the third amplifier circuit to provide an output signal of the multi-stage amplifier;
a first capacitor coupled between the output of the third amplifier circuit and the first input of the second amplifier circuit;
a second capacitor coupled between the output of the third amplifier circuit and the input of the third amplifier circuit; and
a third capacitor coupled between the output of the second amplifier circuit and the second input of the second amplifier circuit.

12. The multi-stage amplifier according to claim 11 , wherein the third capacitor reduces a noise level of the multi-stage amplifier.

13. The multi-stage amplifier according to claim 11 , wherein the third capacitor removes a right-hand-zero of a transfer function of the multi-stage amplifier.

14. The multi-stage amplifier according to claim 11 , further comprising a voltage source coupled to the second input of the second amplifier via a resistor.

15. The multi-stage amplifier according to claim 14 , wherein the second amplifier circuit is DC coupled to the first amplifier circuit, and wherein the third amplifier circuit is DC coupled to the second amplifier circuit.

16. A method of compensating a multi-stage amplifier that includes first, second, and third amplifier circuits coupled in a cascade configuration, the method comprising:
compensating the multi-stage amplifier by using a first compensation network coupled between the output of the third amplifier circuit and a non-inverting input of the second amplifier circuit;
compensating the multi-stage amplifier by using a second compensation network is coupled between the output of the third amplifier circuit and the input of the third amplifier circuit;
compensating the multi-stage amplifier by using a third compensation network coupled between the output of the second amplifier circuit and an inverting input of the second amplifier circuit; and
providing a DC operating point for the second amplifier circuit by coupling a bias voltage source coupled to the inverting input of the second amplifier circuit via a resistor.

17. The method according to claim 16 , wherein the second amplifier circuit is DC coupled to the first amplifier circuit, and wherein the third amplifier circuit is DC coupled to the second amplifier circuit.

18. The method according to claim 16 , wherein the first, second, and third compensation networks comprise, respectively, first, second, and third capacitors.

19. The method according to claim 18 , wherein the third capacitor removes a right-hand-zero of a transfer function of the multi-stage amplifier.

20. The method according to claim 18 , wherein the third capacitor reduces a noise level at the output of the third amplifier circuit.

Assignees

• Silicon Lab Inc

Inventors

• Yuan Gang
• Powell Matthew

Classifications

• H03F1/083

  in transistor amplifiers (H03F1/10 - H03F1/22 take precedence) · CPC title

• H03F2203/45116

  Feedback coupled to the input of the differential amplifier · CPC title

• H03F1/26 Primary

  Modifications of amplifiers to reduce influence of noise generated by amplifying elements · CPC title

• H03F1/086

  with FET's · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title