Variable gain amplifier with improved power supply noise rejection

Patent metadata

Field	Value
Publication number	US-9680418-B2
Application number	US-201514941366-A
Country	US
Kind code	B2
Filing date	Nov 13, 2015
Priority date	Nov 13, 2015
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

A voltage gain amplifier (VGA) configured to have reduced supply noise. The VGA includes first resistor, first FET, and a first current-source coupled between first and second voltage rails. The VGA includes second resistor, second FET, and second current-source coupled between the voltage rails. A variable resistor is coupled between the respective sources of the first and second FETs. Variable capacitors are coupled between the first or a third voltage rail and the sources of the first and second input FETs, respectively. If capacitors are coupled to the first voltage rail, noise cancellation occurs across the gate-to-source voltages of the FETs if an input differential signal applied to the gates of the FETs is derived from a supply voltage at the first voltage rail. If capacitors are coupled to the third rail, supply noise is reduced if the supply voltage at the third rail is generated by a cleaner regulator.

First claim

What is claimed is:

1. An apparatus, comprising:
a first field effect transistor (FET) including a first gate, a first source, and a first drain, wherein the first gate is configured to receive a positive component of a first differential signal, and wherein the first source and the first drain are coupled between a first voltage rail and a second voltage rail;
a second FET including a second gate, a second source, and a second drain, wherein the second gate is configured to receive a negative component of the first differential signal, and wherein the second source and the second drain are coupled between the first voltage rail and the second voltage rail, wherein the positive component and the negative component of the first differential signal are based on a supply voltage at the first voltage rail;
a first capacitor directly coupled between the first voltage rail or a third voltage rail and the first source of the first FET; and
a second capacitor directly coupled between the first voltage rail or the third voltage rail and the second source of the second FET.

2. The apparatus of claim 1 , further comprising a previous stage circuit configured to generate the positive and negative components of the first differential signal based on an input signal.

3. The apparatus of claim 1 , wherein the first and second capacitors are coupled to the third voltage rail, wherein a first supply voltage at the first voltage rail includes more supply noise than a second supply voltage at the third voltage rail.

4. An apparatus, comprising:
a first field effect transistor (FET) including a first gate, a first source, and a first drain, wherein the first gate is configured to receive a positive component of a first differential signal, and wherein the first source and the first drain are coupled between a first voltage rail and a second voltage rail;
a second FET including a second gate, a second source, and a second drain, wherein the second gate is configured to receive a negative component of the first differential signal, and wherein the second source and the second drain are coupled between the first voltage rail and the second voltage rail;
a first capacitor coupled between the first voltage rail or a third voltage rail and the first source of the first FET;
a second capacitor coupled between the first voltage rail or the third voltage rail and the second source of the second FET; and
a voltage divider coupled between the first voltage rail or the third voltage rail and the second voltage rail, wherein the voltage divider is configured to generate a selected bias voltage, wherein the first and second capacitors comprise first and second capacitances based on the selected bias voltage, respectively.

5. The apparatus of claim 1 , wherein the first and second capacitors comprise first and second variable capacitors, respectively.

6. An apparatus, comprising:
a first field effect transistor (FET) including a first gate, a first source, and a first drain, wherein the first gate is configured to receive a positive component of a first differential signal, and wherein the first source and the first drain are coupled between a first voltage rail and a second voltage rail;
a second FET including a second gate, a second source, and a second drain, wherein the second gate is configured to receive a negative component of the first differential signal, and wherein the second source and the second drain are coupled between the first voltage rail and the second voltage rail;
a first capacitor coupled between the first voltage rail or a third voltage rail and the first source of the first FET, wherein the first capacitor comprises a first set of capacitance paths each configured to be selectively coupled between the first voltage rail or the third voltage rail and the first source of the first FET;
a second capacitor coupled between the first voltage rail or the third voltage rail and the second source of the second FET, wherein the second capacitor comprises a second set of capacitance paths each configured to be selectively coupled between the first voltage rail or the third voltage rail and the second source of the second FET.

7. An apparatus, comprising:
a first field effect transistor (FET) including a first gate, a first source, and a first drain, wherein the first gate is configured to receive a positive component of a first differential signal, and wherein the first source and the first drain are coupled between a first voltage rail and a second voltage rail;
a second FET including a second gate, a second source, and a second drain, wherein the second gate is configured to receive a negative component of the first differential signal, and wherein the second source and the second drain are coupled between the first voltage rail and the second voltage rail;
a first capacitor coupled between the first voltage rail or a third voltage rail and the first source of the first FET;
a second capacitor coupled between the first voltage rail or the third voltage rail and the second source of the second FET; and
a resistor coupled between the first source of the first FET and the second source of the second FET.

8. An apparatus, comprising:
a first field effect transistor (FET) including a first gate, a first source, and a first drain, wherein the first gate is configured to receive a positive component of a first differential signal, and wherein the first source and the first drain are coupled between a first voltage rail and a second voltage rail;
a second FET including a second gate, a second source, and a second drain, wherein the second gate is configured to receive a negative component of the first differential signal, and wherein the second source and the second drain are coupled between the first voltage rail and the second voltage rail;
a first capacitor coupled between the first voltage rail or a third voltage rail and the first source of the first FET;
a second capacitor coupled between the first voltage rail or the third voltage rail and the second source of the second FET;
a first resistor coupled between the first voltage rail and the first drain of the first FET;
a second resistor coupled between the first voltage rail and the second drain of the second FET;
wherein a negative component of a second differential signal is generated at a first node between the first resistor and the first drain of the first FET; and
wherein a positive component of the second differential signal is generated at a second node between the second resistor and the second drain of the second FET.

9. The apparatus of claim 1 , further comprising:
a third FET including a third gate, a third source, and a third drain, wherein the third gate is configured to receive a bias voltage configured to set a first current through the third FET, and wherein the third source and the third drain are coupled in series with the first source and the first drain of the first FET between the first voltage rail and the second voltage rail; and
a fourth FET including a fourth gate, a fourth source, and a fourth drain, wherein the fourth gate is configured to receive the bias voltage configured to set a second current through the fourth FET, and wherein the fourth source and the fourth drain are coupled in series with the second source and the second drain of the second FET between the first voltage rail and the second voltage rail.

10. A method, comprising:
applying a positive component of a first differential signal to a first gate of a first field effect transistor (FET), wherein the first FET includes a first source and a first drain coupled between a first voltage rail and a second voltage rail;
applying a negative component of the first differenti

Assignees

• Qualcomm Inc

Inventors

• Yuan Xiaobin
• Natonio Joseph
• Bartholomew Kevin Robert
• Prasad Mangal

Classifications

• H03F2203/45154

  the bias at the input of the amplifying transistors being controlled · CPC title

• H03F1/0211 Primary

  with control of the supply voltage or current · CPC title

• H03F3/45179

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03G3/20 Primary

  Automatic control ({H03G3/005 takes precedence;} combined with volume compression or expansion H03G7/00) · CPC title

• H03F3/45479 Primary

  characterised by the way of common mode signal rejection · CPC title