Organic light emitting display device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9680122-B1
Application number	US-201715425586-A
Country	US
Kind code	B1
Filing date	Feb 6, 2017
Priority date	May 30, 2013
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

An organic light emitting display device may include: a cell array comprising gate lines and data lines intersecting each other on a substrate so as to define a plurality of pixel areas, a plurality of thin film transistors formed at intersections between the gate lines and the data lines to correspond to the plurality of pixel areas, and a protective film evenly formed over the substrate to cover the thin film transistors; a plurality of first electrodes formed such that portions of an metal oxide layer corresponding to emission areas of the respective pixel areas, is made conductive, the metal oxide layer evenly disposed on the protective film; a bank constituting the remaining portion of the metal oxide layer in which the first electrodes are not formed and formed so as to have insulating properties; an emission layer formed over the metal oxide layer; and a second electrode formed on the emission layer so as to face the first electrodes.

First claim

What is claimed is:

1. A method of manufacturing an organic light emitting display device, the method comprising:
arranging a cell array on a substrate, the cell array comprising gate lines and data lines intersecting each other so as to define a plurality of pixel areas, a plurality of thin film transistors corresponding to the plurality of pixel areas, and a protective film evenly formed and covering the plurality of thin film transistors;
forming a metal oxide layer evenly on the protective film, consisting of a plurality of first electrodes and insulation portions arranged at both sides of the first electrodes, wherein an upper surface of the plurality of first electrodes and an upper surface of the insulating portions of the metal oxide layer are coplanar;
forming a planar emission layer directly on the entire upper surface of the insulation portions and the entire upper surface of the first electrodes of the metal oxide layer; and
forming a second electrode on the planar emission layer to face the first electrodes.

2. The method according to claim 1 , wherein, in the forming of the metal oxide layer, the metal oxide layer comprises A x B y C z O (x, y, z>0), wherein A, B and C are each independently selected from among Zn, Cd, Ga, In, Sn, Hf, and Zr and is formed by deposition so as to have insulating properties.

3. The method according to claim 2 , wherein the metal oxide layer comprises one selected from among In—Ga—Zn—Oxide (IGZO), In—Sn—Zn-Oxide (ITZO), and In—Ga-Oxide (IGO).

4. The method according to claim 2 , wherein the forming of the first electrodes and the forming of the bank comprises:
forming a mask on the metal oxide layer, the mask having openings corresponding to the emission areas of the respective pixel areas; and
selectively performing plasma treatment on the metal oxide layer using the mask such that portions of the metal oxide layer corresponding to the emission areas of the respective pixel area form the plurality of first electrodes having the conductive properties through the plasma treatment, and the remaining portion of the metal oxide layer forms the bank.

5. The method according to claim 4 , wherein the plasma treatment for the portions of the metal oxide layer is performed using a gas comprising at least one of Ar, N 2 , and H 2 .

6. The method according to claim 1 , wherein the arranging the cell array comprises:
forming the gate lines and gate electrodes connected to the gate lines on the substrate;
forming a gate insulating film over the substrate so as to cover the gate lines and the gate electrodes;
forming an active layer on the gate insulating film to overlap with at least a portion of the gate electrodes;
forming the data lines and the source and drain electrodes on the gate insulating film, the source and drain electrodes respectively overlapping with opposite sides of the active layer and spaced apart from each other; and
forming the protective film over the gate insulating film so as to cover the source and drain electrodes and have a flat upper surface.

7. The method according to claim 6 , further comprising, before the forming of the metal oxide layer,
forming a contact hole passing through at least the protective film so as to expose a portion of any one of the source and drain electrodes,
wherein each first electrode is connected to any one of the source and drain electrodes via the contact hole.

8. The method according to claim 7 , further comprising, after the formed of the contact hole and before the forming of the metal oxide layer,
forming a sub-electrode corresponding to the emission areas of the respective pixel area of each pixel area, and disposed between the first electrode and the protective film to cover at least the contact hole.

Assignees

• Lg Display Co Ltd

Inventors

• Seo Hyun-Sik
• Kim Jong-Woo
• Seo Kyung-Han

Classifications

• H10K59/8051

  Anodes · CPC title

• H10K50/81

  Anodes · CPC title

• H10K71/211 Primary

  by selective transformation of an existing layer · CPC title

• H01L2227/323

  Electricity · mapped topic

• H01L51/0021

  Electricity · mapped topic