Plated electrical contacts for solar modules

Patent metadata

Field	Value
Publication number	US-9680042-B2
Application number	US-201314650342-A
Country	US
Kind code	B2
Filing date	Dec 16, 2013
Priority date	Jan 17, 2013
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

The present invention concerns a plating method for manufacturing of electrical contacts on a solar module wherein the wiring between silicon solar cells in a solar module is deposited by electroplating onto a conductive seed. The wiring between individual silicon solar cells comprises wiring reinforcement pillars which improve the reliability of said wiring.

First claim

The invention claimed is:

1. A plating method for manufacturing of electrical contacts on a solar module, the method comprising, in this order, the steps of
(i) providing an array of silicon solar cells mounted onto a support substrate, the silicon solar cells separated from each other by a horizontal spacing, and having an exposed surface comprising at least one contact area on each silicon solar cell,
(ii) depositing a plating resist onto the exposed surface of the array of silicon solar cells and the horizontal spacing between the solar cells,
(iii) forming openings in the plating resist and thereby expose the at least one contact area on each silicon solar cell and at least one portion of the horizontal spacing between the silicon solar cells,
(iv) forming a conductive seed layer on top of the plating resist and the openings formed in step (iii),
(v) forming a copper or copper alloy layer on top of the conductive seed layer, and
(vi) etching back those portions of the copper or copper alloy layer and the conductive seed layer sufficient to remove both the copper or copper alloy layer and the conductive seed layer from the plating resist leaving a copper or copper alloy layer in the openings formed in step (iii) and thereby forming a wiring between silicon solar cells and wiring reinforcement pillars.

2. The method according to claim 1 wherein the silicon solar cells are single crystalline silicon solar cells, poly crystalline silicon solar cells or amorphous silicon solar cells.

3. The method according to claim 1 wherein the silicon solar cells are silicon-based back-contact cells wherein all of the wiring on and between individual cells is attached to the backside of the silicon solar cells.

4. The method according to claim 1 wherein the support substrate consists of a glass layer and an encapsulant which is in contact with the array of silicon solar cells.

5. The method according to claim 1 wherein the horizontal spacing width ranges from 0.5 to 20 mm.

6. The method according to claim 1 wherein the plating resist is deposited by a method selected from curtain coating, screen printing, roller coating, dry lamination and spray coating.

7. The method according to claim 1 wherein the plating resist comprises one or more of acrylates, ethylene/ethylacrylate copolymer, ethylene/methacrylate copolymer, ethylene/acrylic acid copolymer, ethylene/butylacrylate copolymer, polymethylpentene, and polymethylmethacrylate.

8. The method according to claim 1 wherein the plating resist comprises a filler selected from the group consisting of aluminium borate, aluminium oxide, aluminiumtrihydroxide, anthracite, sodium antimonate, antimony pentoxide, antimony trioxide, apatite, attapulgite, barium metaborate, barium sulfate, strontium sulfate, barium titanate, bentonite, beryllium oxide, boron nitride, calcium carbonate, calcium hydroxide, calcium sulfate, carbon black, clay, cristobalite, diatomaceous earth, dolomite, ferrites, feldspar, glass beads, graphite, hydrous calcium silicate, iron oxide, kaolin, lithopone, magnesium oxide, mica, molybdenum disulfide, perlite, polymeric fillers such as PTFE, PE, polyimide, pumice, pyrophyllite, rubber particles, fumed silica, fused silica, precipitated silica, sepiolite, quartz, sand, slate flour, talc, titanium dioxide, vermiculite, wood flour, wollastonite, zeolites, zinc borate, zinc oxide, zinc stannate, zinc sulfide, aramid fibers, carbon fibers, cellulose fibers, and glass fibers, and mixtures thereof.

9. The method according to claim 1 wherein the conductive seed layer is formed by a method selected from the group consisting of electroless plating, direct plating, physical vapour deposition, chemical vapour deposition and plasma enhanced chemical vapour deposition.

10. The method according to claim 1 wherein the conductive seed layer is selected from the copper, copper alloys, nickel and nickel alloys.

11. The method according to claim 1 wherein the copper or copper alloy layer is deposited by electroplating.

12. The method according to claim 1 wherein the patterned plating resist layer is removed after step (vi).

13. The method according to claim 1 wherein, in step (iii), first openings are formed in the horizontal spacing between at least two of the silicon solar cells for the wiring reinforcement pillars and second openings are formed for the wiring between the at least two silicon solar cells by exposing at least a portion of the contact areas.

14. The method according to claim 1 wherein, in step (iv), the conductive seed layer is deposited onto at least a portion of the contact area exposed by the second openings, onto the outer surface of the patterned plating resist layer and onto those portions of the encapsulant which are exposed by the first openings.

15. The method according to claim 1 wherein no direct contact with the side walls of the silicon solar cells and the copper or copper alloy layer is formed.

16. The method according to claim 1 ,
wherein, in step (iii), first openings are formed in the horizontal spacing between at least two of the silicon solar cells for the wiring reinforcement pillars and second openings are formed for the wiring between the at least two silicon solar cells by exposing at least a portion of the contact areas;
wherein, in step (iv), the conductive seed layer is deposited onto at least a portion of the contact area exposed by the second openings, onto the outer surface of the patterned plating resist layer and onto those portions of the encapsulant which are exposed by the first openings; and
wherein no direct contact with the side walls of the silicon solar cells and the copper or copper alloy layer is formed.

Assignees

• Atotech Deutschland Gmbh

Inventors

• Voss Torsten
• Lamprecht Sven

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title