Method for fabricating a metal high-k gate stack for a buried recessed access device

Patent metadata

Field	Value
Publication number	US-9680007-B2
Application number	US-201615072472-A
Country	US
Kind code	B2
Filing date	Mar 17, 2016
Priority date	May 31, 2013
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

A method for fabricated a buried recessed access device comprising etching a plurality of gate trenches in a substrate, implanting and activating a source/drain region in the substrate, depositing a dummy gate in each of the plurality of gate trenches, filling the plurality of gate trenches with an oxide layer, removing each dummy gate and depositing a high-K dielectric in the plurality of gate trenches, depositing a metal gate on the high-K dielectric in each of the plurality of gate trenches, depositing a second oxide layer on the metal gate and forming a contact on the source/drain.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a plurality of trenches formed in the substrate;
a plurality of regions formed in the substrate, wherein each region is separated from an adjacent region by one of the trenches;
a plurality of electrodes, wherein each region in the plurality of regions includes an electrode, and wherein each of the electrodes is electrically isolated from the other electrodes;
a plurality of metal gates, wherein a metal gate is located in an end of each of the trenches opposite a first surface of the substrate;
a plurality of oxide layers, wherein an oxide layer is located in an end of each of the trenches adjacent the first surface of the substrate.

2. The semiconductor device of claim 1 , wherein the trenches extend from a first surface of the substrate.

3. The semiconductor device of claim 1 , wherein for each region the included electrode is located between each of the regions and the first surface of the substrate.

4. The semiconductor device of claim 1 , wherein each of the electrodes extends at least a first distance from the surface of the substrate.

5. The semiconductor device of claim 4 , wherein each of the oxide layers extends at least a second distance from the first surface of the substrate, and wherein the first distance is less than the second distance.

6. The semiconductor device of claim 1 , further comprising:
a plurality of silicide layers, wherein a silicide layer is located in each of the trenches, and wherein in each trench the silicide layer separates the metal gate from the oxide layer.

7. The semiconductor device of claim 1 , wherein the regions are source/drain regions.

8. The semiconductor device of claim 1 , further comprising:
a plurality of dielectric layers, wherein each of the trenches includes a dielectric layer.

9. The semiconductor device of claim 1 , further comprising:
a plurality of silicide layers, wherein for each of the trenches a silicide layer is disposed between the metal gate and the oxide layer.

10. The semiconductor device of claim 1 , wherein the plurality of regions are each source/drain regions.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Mayuzumi Satoru
• Fischer Mark
• Violette Michael

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01316

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al · CPC title

• H10D64/013 Primary

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title