Junction-less insulated gate current limiter device

Patent metadata

Field	Value
Publication number	US-9679890-B2
Application number	US-201414454435-A
Country	US
Kind code	B2
Filing date	Aug 7, 2014
Priority date	Aug 9, 2013
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

In one general aspect, an apparatus can include a semiconductor substrate, and a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis. The apparatus includes a dielectric disposed within the trench, and an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric. The semiconductor substrate can have a portion aligned vertically and adjacent the trench, and the portion of the semiconductor substrate can have a conductivity type that is continuous along an entirety of the depth of the trench. The apparatus is biased to a normally-on state.

First claim

What is claimed is:

1. An apparatus, comprising:
a semiconductor substrate;
a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis;
a dielectric disposed within the trench; and
an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric,
the semiconductor substrate having a portion aligned vertically and adjacent the trench, the portion of the semiconductor substrate having a conductivity type that is continuous along an entirety of the depth of the trench, the apparatus being biased to a normally-on state.

2. The apparatus of claim 1 , wherein the portion is a first portion of a mesa, the mesa has a second portion including a PN junction.

3. The apparatus of claim 1 , further comprising:
a source conductor disposed on a first side of the semiconductor substrate; and
a drain conductor disposed on a second side of the semiconductor substrate opposite the first side of the semiconductor substrate.

4. The apparatus of claim 1 , further comprising:
a source conductor disposed on a first side of the semiconductor substrate; and
a drain conductor disposed on a second side of the semiconductor substrate opposite the first side of the semiconductor substrate,
the portion of the semiconductor substrate having the conductivity type extending between the source conductor and the drain conductor.

5. The apparatus of claim 1 , further comprising:
a source conductor disposed on a top surface of the semiconductor substrate, the dielectric having a portion disposed between the source conductor and the electrode.

6. The apparatus of claim 1 , further comprising:
a source conductor disposed on a top surface of the semiconductor substrate, the dielectric having a portion coupled to the source conductor and coupled to the electrode.

7. The apparatus of claim 1 , wherein the conductivity type is an N-type conductivity, the electrode has the N-type conductivity.

8. The apparatus of claim 1 , wherein the apparatus is a junctionless device.

9. The apparatus of claim 1 , wherein the portion of the semiconductor substrate is a first portion of the semiconductor substrate,
the apparatus further comprising:
a source conductor disposed on a first side of the semiconductor substrate and coupled to a first portion of the dielectric; and
a drain conductor disposed on a second side of the semiconductor substrate opposite the first side of the semiconductor substrate, the drain conductor being separated from a second portion of the dielectric by a second portion of the semiconductor substrate, the electrode being coupled to the source conductor.

10. The apparatus of claim 1 , wherein the dielectric has a first portion aligned vertically and a second portion aligned horizontally,
the apparatus further comprising:
a first space charge region in contact with the first portion; and
a second space charge region in contact with the second portion.

11. The apparatus of claim 1 , wherein the apparatus is configured to limit current to a saturation current in response to voltage drop across the semiconductor substrate.

12. The apparatus of claim 1 , further comprising:
a source conductor having at least a portion disposed on a top surface of the semiconductor substrate and directly coupled to the electrode.

13. The apparatus of claim 1 , further comprising:
a source conductor having at least a portion directly coupled to the electrode.

14. A method, comprising:
removing a plurality of charges from a region in contact with an interface between a dielectric and a semiconductor substrate in response to a difference between a voltage applied to a source conductor and a voltage applied to a drain conductor increasing; and
blocking at least a portion of a current between the source conductor and the drain conductor via the removing the plurality of charges from the region.

15. The method of claim 14 , wherein the region is a first region, the interface is a first interface, the plurality of charges includes a first plurality of charges,
the method further comprising:
removing a second plurality of charges from a second region in contact with a second interface between the dielectric and the semiconductor substrate, the second interface being substantially orthogonal to the first interface.

16. The method of claim 14 , wherein the voltage applied to the source conductor is substantially equal to a voltage applied to an electrode in contact with the dielectric.

17. The method of claim 14 , wherein the voltage applied to the drain conductor is greater than the voltage applied to the source conductor.

18. The method of claim 14 , further comprising:
increasing a current within the region, the region has a resistance that increases in response to the increasing current.

19. An apparatus, comprising:
a semiconductor substrate;
a trench defined within the semiconductor substrate and having a depth aligned along a vertical axis, a length aligned along a longitudinal axis, and a width aligned along a horizontal axis;
a dielectric disposed within the trench; and
an electrode disposed within the dielectric and insulated from the semiconductor substrate by the dielectric,
the semiconductor substrate having a portion aligned vertically and adjacent the trench, the portion of the semiconductor substrate having a conductivity type that is continuous along an entirety of the depth of the trench, the apparatus being biased to an on-state.

20. The apparatus of claim 19 , further comprising:
a source conductor disposed on a first side of the semiconductor substrate; and
a drain conductor disposed on a second side of the semiconductor substrate opposite the first side of the semiconductor substrate.

Assignees

• Fairchild Semiconductor

Inventors

• Sarkar Tirthajyoti
• Mikolajczak Adrian
• Ho Ihsiu
• Challa Ashok

Classifications

• H01L29/861

  Electricity · mapped topic

• H01L29/408

  Electricity · mapped topic

• H01L29/66166

  Electricity · mapped topic

• H01L27/0266

  Electricity · mapped topic

• H01L29/6606

  Electricity · mapped topic