Semiconductor device and method including an intertial mass element

Patent metadata

Field	Value
Publication number	US-9679857-B2
Application number	US-201615266809-A
Country	US
Kind code	B2
Filing date	Sep 15, 2016
Priority date	Jul 15, 2009
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

Disclosed is a semiconductor device comprising a stack of patterned metal layers separated by dielectric layers, the stack comprising a first conductive support structure and a second conductive support structure and a cavity in which an inertial mass element comprising at least one metal portion is conductively coupled to the first support structure and the second support structure by respective conductive connection portions, at least one of said conductive connection portions being designed to break upon the inertial mass element being exposed to an acceleration force exceeding a threshold defined by the dimensions of the conductive connection portions. A method of manufacturing such a semiconductor device is also disclosed.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a stack of patterned metal layers separated by dielectric layers, the dielectric layers having a first plurality of conductive vias that connect metal layers adjacent to the dielectric layers, the stack comprising:
a first conductive support structure having a first metal layer and a second conductive support structure having a second metal layer;
a cavity between the first conductive support structure and the second conductive support structure;
an inertial mass element having at least one metal portion which is vertically displaced with respect to the first metal layer and the second metal layer; and
a first plurality of conductive connection vias that conductively couple the inertial mass element to the first metal layer and the second metal layer, wherein at least one of the first plurality of conductive connection vias is configured to break upon the inertial mass element being exposed to an acceleration force exceeding a threshold defined by dimensions of the first plurality of conductive connection vias.

2. The semiconductor device of claim 1 , further comprising:
a detector configured to detect a disruption in the conductive coupling of the inertial mass element to the first metal layer and the second metal layer.

3. The semiconductor device of claim 1 , wherein the inertial mass element is below the first metal layer and the second metal layer.

4. The semiconductor device of claim 1 , wherein the inertial mass element is above the first metal layer and the second metal layer.

5. The semiconductor device of claim 4 , wherein the first plurality of vias connect the inertial mass element to the first metal layer and the second metal layer near a first lateral end of the inertial mass element and a first force applied to a second lateral end of the inertial mass element applies a second force to one of the first plurality of vias in a substantially opposite direction of the applied first force.

6. The semiconductor device of claim 1 , wherein the inertial mass element is between the first metal layer and the second metal layer.

7. The semiconductor device of claim 1 , wherein the inertial mass element has a plurality of perforations extending through the inertial mass element.

8. The semiconductor device of claim 1 , wherein the inertial mass element comprises a stack of metal layer portions separated by dielectric layer portions and each of the dielectric layer portions comprises a second plurality of vias configured to conductively interconnect the stack of metal layer portions.

9. The semiconductor device of claim 1 , wherein the stack comprises a plurality of cavities each comprising a respective inertial mass element conductively coupled to the first metal layer and the second metal layer by the first plurality of vias and at least one of the first plurality of vias associated respectively with each cavity is configured to break upon the respective inertial mass element being exposed to an acceleration force exceeding a threshold that is unique to that respective cavity.

10. A method of manufacturing a semiconductor device, comprising:
forming a stack of patterned metal layers separated by dielectric layers, the stack comprising a first conductive support structure having a first metal layer, a second conductive support structure having a second metal layer, and an inertial mass element comprising at least one metal portion and a first plurality of conductive connection vias that conductively couple the inertial mass element to the first metal layer and the second metal layer, wherein at least one of the first plurality of conductive connection vias is configured to break upon the inertial mass element being exposed to an acceleration force exceeding a threshold defined by dimensions of the first plurality of conductive connection vias;
forming a passivation layer over the stack;
selectively removing the passivation layer over an area comprising the inertial mass element to form an exposed area; and
etching the exposed area to form a cavity around the inertial mass element.

11. The method of claim 10 , wherein the stack comprises a perforated metal portion extending over the inertial mass element and at least partially extending over the first conductive support structure and the second conductive support structure and the etching step is performed through perforations of the perforated metal portion.

Assignees

• Merz Matthias
• Ponomarev Youri Victorovitch
• Van Dal Mark
• Nxp Bv

Inventors

• Merz Matthias
• Ponomarev Youri Victorovitch
• Van Dal Mark

Classifications

• H10W20/493

  Fuses, i.e. interconnections changeable from conductive to non-conductive · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title