Cross-point memory compensation

Patent metadata

Field	Value
Publication number	US-9679642-B2
Application number	US-201514739798-A
Country	US
Kind code	B2
Filing date	Jun 15, 2015
Priority date	Oct 10, 2011
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

First claim

What is claimed is:

1. A method, comprising:
measuring a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array;
comparing the measured voltage difference with a reference voltage specified for a memory operation;
adjusting a selection voltage applied to the selected cell for the memory operation to provide an adjusted selection voltage responsive to the comparison; and
refraining from at least one of the measuring, comparing, or adjusting acts in response to the selected cell being located in a specified area of the memory array.

2. The method of claim 1 , wherein the measuring comprises coupling the selected cell to a volt-meter configured to measure the voltage difference between the selected access lines and the selected sense lines.

3. The method of claim 2 , wherein the coupling comprising coupling the selected access line and the selected sense line to the volt-meter via a compensation row decoder and a compensation column decoder, respectively.

4. The method of claim 1 , wherein the comparing comprises reading a value of the reference voltage from a register.

5. The method of claim 1 , wherein the adjusting comprises increasing the selection voltage.

6. The method of claim 1 , wherein the memory operation comprises at least one operation selected from operations including a set operation, a reset operation, and a read operation.

7. The method of claim 1 , further comprising determining whether the selected cell is located closer to a corresponding driver supplying the selection voltage than a threshold distance.

8. The method of claim 1 , further comprising activating a sense amplifier to complete the memory operation responsive to determining that the measured voltage difference is at least substantially equal to the reference voltage.

9. A method, comprising:
measuring, during a first pulse of a memory operation, a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array;
comparing the measured voltage difference with a reference voltage specified for the memory operation;
adjusting, during a second pulse of the memory operation, a selection voltage applied to the selected cell for the memory operation to provide an adjusted selection voltage responsive to the comparison; and
refraining from at least one of the measuring, comparing or adjusting acts in response to the selected cell being located in a specified area of the memory array.

10. The method of claim 9 , further comprising readjusting the adjusted selection voltage during a third pulse of the memory operation.

11. The method of claim 10 , further comprising adjusting the reference voltage for at least one of the second pulse or the third pulse.

12. The method of claim 9 , wherein the measured voltage difference includes a voltage drop at a location of each of the plurality of memory cells due to a parasitic voltage drop for each of the selected access line and the selected sense line at a respective cross-point associated with the selected cell.

13. A method, comprising:
measuring a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array for each memory operation, the measured voltage difference to include measuring a voltage drop at a location of each of the plurality of memory cells due to a parasitic voltage drop for each of the selected access line and the selected sense line at a respective cross-point associated with the selected cell;
comparing the measured voltage difference with a reference voltage specified for a memory operation; and
adjusting a selection voltage applied to the selected cell for the memory operation to provide an adjusted selection voltage responsive to the comparison.

14. A method, comprising:
measuring, during a first pulse of a memory operation, a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array, the measured voltage difference including a voltage drop at a location of each of the plurality of memory cells due to a parasitic voltage drop for each of the selected access line and the selected sense line at a respective cross-point associated with the selected cell;
comparing the measured voltage difference with a reference voltage specified for the memory operation; and
adjusting, during a second pulse of the memory operation, a selection voltage applied to the selected cell for the memory operation to provide an adjusted selection voltage responsive to the comparison.

Assignees

• Micron Technology Inc

Inventors

• Liu Zengtao T
• Prall Kirk D

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C13/003

  Cell access · CPC title

• G11C13/0038

  Power supply circuits · CPC title