Two part programming and erase methods for non-volatile charge trap memory devices

Patent metadata

Field	Value
Publication number	US-9679639-B2
Application number	US-201615040175-A
Country	US
Kind code	B2
Filing date	Feb 10, 2016
Priority date	Sep 14, 2015
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation or erase operation of the memory cell array; and a control logic controlling the peripheral circuit. The control logic controls the peripheral circuit such that a first program allowable voltage applied to bit lines of the memory cell array during a first program operation of the program operation and a second program allowable voltage applied during a second program operation of the program operation are different from each other.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells;
a peripheral circuit configured to perform a program operation or erase operation of the memory cell array; and
a control logic configured to control the peripheral circuit such that a first erase control voltage applied to word lines of the memory cell array during a first erase operation of the erase operation and a second erase control voltage applied to the word lines during a second erase operation of the erase operation are different from each other,
wherein the peripheral circuit comprises a voltage generator configured to generate a set erase voltage to be applied to a source line of the memory cell array during the first erase operation and normal erase voltages to be applied to the source line during the second erase operation, and
wherein the set erase voltage has a longer application time than a first normal erase voltage of the normal erase voltages.

2. The semiconductor memory device according to claim 1 ,
wherein the control logic controls the peripheral circuit such that a first program allowable voltage applied to bit lines of the memory cell array during a first program operation of the program operation and a second program allowable voltage applied during a second program operation of the program operation are different from each other, and
wherein the first program allowable voltage has a lower potential level than the second program allowable voltage.

3. The semiconductor memory device according to claim 2 ,
wherein
the voltage generator configured to generate a set program voltage to be applied to word lines of the memory cell array during the first program operation, and normal program voltages to be applied to the word lines during the second program operation, and
wherein the peripheral circuit further comprises:
a reading and writing circuit configured to apply the first program allowable voltage and second program allowable voltage to the bit lines during the first program operation and second program operation.

4. The semiconductor memory device according to claim 3 ,
wherein the set program voltage has a higher potential level than a first normal program voltage of the normal program voltages.

5. The semiconductor memory device according to claim 3 ,
wherein the set program voltage has a longer application time than a first normal program voltage of the normal program voltages.

6. The semiconductor memory device according to claim 3 ,
wherein the voltage generator generates a set program voltage having a different potential level and different application time.

7. The semiconductor memory device according to claim 2 ,
wherein the first program operation is performed before the second program operation is performed.

8. The semiconductor memory device according to claim 1 ,
wherein the first erase control voltage has a lower potential level than the second erase control voltage.

9. The semiconductor memory device according to claim 1 ,
wherein the set erase voltage has a higher potential level than the first normal erase voltage of the normal erase voltages.

10. The semiconductor memory device according to claim 1 ,
wherein the voltage generator generates a set erase voltage having a different potential level and different application time.

11. The semiconductor memory device according to claim 1 ,
wherein the first erase operation is performed before the second erase operation is performed.

Assignees

• Sk Hynix Inc

Inventors

• Lee Yeonghun

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C11/5628 Primary

  Programming or writing circuits; Data input circuits · CPC title