Techniques for optimizing stencil buffers

Patent metadata

Field	Value
Publication number	US-9679350-B2
Application number	US-201514817151-A
Country	US
Kind code	B2
Filing date	Aug 3, 2015
Priority date	Jul 15, 2013
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

One embodiment sets forth a method for associating each stencil value included in a stencil buffer with multiple fragments. Components within a graphics processing pipeline use a set of stencil masks to partition the bits of each stencil value. Each stencil mask selects a different subset of bits, and each fragment is strategically associated with both a stencil value and a stencil mask. Before performing stencil actions associated with a fragment, the raster operations unit performs stencil mask operations on the operands. No fragments are associated with both the same stencil mask and the same stencil value. Consequently, no fragments are associated with the same stencil bits included in the stencil buffer. Advantageously, by reducing the number of stencil bits associated with each fragment, certain classes of software applications may reduce the wasted memory associated with stencil buffers in which each stencil value is associated with a single fragment.

First claim

What is claimed is:

1. A computer-implemented method for generating a stencil buffer, the method comprising:
determining a first number of regions into which a first surface included in a memory should be divided based on a number of stencil bits defined per sample and a number of bits defined per stencil value;
dividing the first surface included in the memory into the first number of regions;
associating each region included in the first number of regions with a different stencil mask; and
mapping virtual memory addresses associated with the first number of regions to a set of physical memory addresses associated with the first surface.

2. The method of claim 1 , further comprising:
selecting a first region included in the plurality of regions based on a set of screen-space coordinates;
determining a first stencil mask associated with the first region; and
selecting one or more stencil bits included in the first stencil value based on the first stencil mask.

3. The method of claim 2 , wherein the screen-space coordinates are associated with a first sample, a first cache tile, or a first raster tile.

4. The method of claim 1 , wherein one stencil bit is designated per sample.

5. The method of claim 1 , wherein two stencil bits or four stencil bits are designated per sample.

6. The method of claim 1 , wherein the memory comprises a stencil buffer.

7. The method of claim 1 , further comprising:
associating a first region included in the plurality of regions with a first stencil mask; and
mapping surface coordinates of a first fragment to a first virtual address included in a virtual address space, wherein the first fragment resides within the first region.

8. The method of claim 7 , further comprising:
selecting a first stencil value based on the first virtual address; and
performing a logical operation between the first stencil mask and the first stencil value to associate the first fragment with the first number of bits included in the first stencil mask.

9. A system, comprising:
a memory that includes a stencil buffer;
a memory management unit coupled to the memory;
a tiling unit coupled to the memory management unit; and
a raster operations unit coupled to the memory management unit, wherein at least one of the tiling unit and the raster operations unit is configured to:
determine a first number of regions into which a first surface included in a memory should be divided based on a number of stencil bits defined per sample and a number of bits defined per stencil value;
divide the first surface included in the memory into the first number of regions;
associate each region included in the first number plurality of regions with a different stencil mask; and
map virtual memory addresses associated with the first number of regions to a set of physical memory addresses associated with the first surface.

10. The system of claim 9 , wherein at least one of the tiling unit and the raster operations unit is further configured to:
select a first region included in the plurality of regions based on a set of screen-space coordinates;
determine a first stencil mask associated with the first region; and
select one or more stencil bits included in the first stencil value based on the first stencil mask.

11. The system of claim 10 , wherein the screen-space coordinates are associated with a first sample, a first cache tile, or a first raster tile.

12. The system of claim 9 , wherein one stencil bit is designated per sample.

13. The system of claim 9 , wherein two stencil bits or four stencil bits are designated per sample.

14. The system of claim 9 , wherein at least one of the tiling unit and the raster operations unit is further configured to:
associate a first region included in the plurality of regions with a first stencil mask; and
map surface coordinates of a first fragment to a first virtual address included in a virtual address space, wherein the first fragment resides within the first region.

15. The system of claim 14 , wherein at least one of the tiling unit and the raster operations unit is further configured to:
select a first stencil value based on the first virtual address; and
perform a logical operation between the first stencil mask and the first stencil value to associate the first fragment with the first number of bits included in the first stencil mask.

16. A non-transitory computer-readable storage medium including instructions that, when executed by a processor, configure the processor to perform the steps of:
determining a first number of regions into which a first surface included in a memory should be divided based on a number of stencil bits defined per sample and a number of bits defined per stencil value;
dividing the first surface included in the memory into the first number of regions;
associating each region included in the first number of regions with a different stencil mask; and
mapping virtual memory addresses associated with the first number of regions to a set of physical memory addresses associated with the first surface.

17. The computer-readable storage medium of claim 16 , wherein each stencil mask includes a number of bits equal to the number of stencil bits defined per sample.

Assignees

• Nvidia Corp
• Nvdia Corp

Inventors

• Lum Eric B
• Duluk Jr Jerome F

Classifications

• B41F15/34

  Screens, Frames; Holders therefor · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06T15/005

  General purpose rendering architectures · CPC title

• G06T11/40

  Filling planar surfaces by adding surface attributes, e.g. adding colours or textures · CPC title