Serial communication control circuit

Patent metadata

Field	Value
Publication number	US-9678915-B2
Application number	US-201414271609-A
Country	US
Kind code	B2
Filing date	May 7, 2014
Priority date	May 8, 2013
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

In a serial communication control circuit, serial data transmitted from a transmission processing unit is switched to data generated in a mark ratio improvement data generation unit depending on a switch signal from the transmission processing unit, and is transmitted. Thereby, mark ratio improvement data is inserted in a transmission signal to improve a mark ratio during communication, thereby preventing reception signal's jitters from increasing.

First claim

The invention claimed is:

1. A serial communication control circuit for transmitting and receiving encoded data including forward packets, the serial communication control circuit comprising:
a transmission processing unit configured to generate the forward packets of serial data to be transmitted, the transmission processing unit being configured to determine a time period when none of the forward packets is transmitted;
a mark ratio improvement data generation unit configured to generate mark ratio improvement data in addition to the generated forward packets of the serial data; and
a transmission data switch unit configured to
transmit the forward packets of the serial data transmitted from the transmission processing unit, and
in response to a switch signal output from the transmission processing unit, switch the forward packets of the serial data to the mark ratio improvement data generated in the mark ratio improvement data generation unit,

wherein the transmission processing unit is configured to generate the switch signal, in the time period when none of the forward packets is transmitted.

2. The serial communication control circuit according to claim 1 , further comprising:
a mark ratio detection unit configured to detect a mark ratio of transmission data output from the transmission data switch unit,
wherein the mark ratio improvement data generation unit is further configured to
receive the detected mark ratio output from the mark ratio detection unit, and
generate the mark ratio improvement data in accordance with the detected mark ratio.

3. The serial communication control circuit according to claim 2 , wherein the mark ratio detection unit is configured to count the mark ratio in a digital manner.

4. The serial communication control circuit according to claim 2 , wherein the mark ratio detection unit is configured to count the mark ratio in an analog manner.

5. The serial communication control circuit according to claim 1 , wherein the mark ratio improvement data includes
(1) data with a disparity of 0 and a mark ratio of 50%,
(2) data with a disparity of −2 and a mark ratio of 40%, and
(3) data with a disparity of +2 and a mark ratio of 60%.

6. The serial communication control circuit according to claim 2 , wherein the mark ratio improvement data generation unit is configured to use, as the mark ratio improvement data to be generated:
mark ratio improvement data with a mark ratio of 40% when the detected mark ratio is 55% or more,
mark ratio improvement data with a mark ratio of 60% when the detected mark ratio is 45% or less, and
mark ratio improvement data with a mark ratio of 50% when the detected mark ratio is between 45% and 55%.

7. The serial communication control circuit according to claim 1 , wherein the transmission data switch unit configured to insert the mark ratio improvement data between the forward packets at a random interval.

8. A serial communication control circuit for transmitting and receiving encoded data including forward packets, the serial communication control circuit comprising:
a transmission processing unit configured to generate the forward packets of serial data to be transmitted;
a mark ratio improvement data generation unit configured to generate mark ratio improvement data in addition to the generated forward packets of the serial data; and
a transmission data switch unit configured to
transmit the forward packets of the serial data transmitted from the transmission processing unit, and
in response to a switch signal output from the transmission processing unit, switch the forward packets of the serial data to the mark ratio improvement data generated in the mark ratio improvement data generation unit,

wherein the transmission processing unit is configured to generate the switch signal at a time when an empty field of one of the forward packets starts.

9. The serial communication control circuit according to claim 8 , wherein
the transmission processing unit is configured to generate the switch signal at the time when the empty field of one of the forward packets starts within a period determined by a specification according to a communication protocol that ensures a real-time property.

10. The serial communication control circuit according to claim 8 , further comprising:
a mark ratio detection unit configured to detect a mark ratio of transmission data output from the transmission data switch unit,
wherein the mark ratio improvement data generation unit is further configured to
receive the detected mark ratio output from the mark ratio detection unit, and
generate the mark ratio improvement data in accordance with the detected mark ratio.

11. The serial communication control circuit according to claim 10 , wherein the mark ratio detection unit is configured to count the mark ratio in a digital manner.

12. The serial communication control circuit according to claim 10 , wherein the mark ratio detection unit is configured to count the mark ratio in an analog manner.

13. The serial communication control circuit according to claim 10 , wherein the mark ratio improvement data generation unit is configured to use, as the mark ratio improvement data to be generated:
mark ratio improvement data with a mark ratio of 40% when the detected mark ratio is 55% or more,
mark ratio improvement data with a mark ratio of 60% when the detected mark ratio is 45% or less, and
mark ratio improvement data with a mark ratio of 50% when the detected mark ratio is between 45% and 55%.

14. The serial communication control circuit according to claim 8 , wherein the mark ratio improvement data includes
(1) data with a disparity of 0 and a mark ratio of 50%,
(2) data with a disparity of −2 and a mark ratio of 40%, and
(3) data with a disparity of +2 and a mark ratio of 60%.

Assignees

• Fanuc Corp

Inventors

• Miura Masahiro

Classifications

• G06F13/42 Primary

  Bus transfer protocol, e.g. handshake; Synchronisation · CPC title

• G06F13/4295

  using an embedded synchronisation · CPC title

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title