Data processing apparatus

Patent metadata

Field	Value
Publication number	US-9678902-B2
Application number	US-201314070293-A
Country	US
Kind code	B2
Filing date	Nov 1, 2013
Priority date	Jan 15, 2013
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

A concurrent flag set (changed from a first state to a second state) when generating a plurality of event signals at the same time from one circuit module that operates synchronously is prepared. When it is determined that the concurrent event signals are generated with reference to the concurrent flag, processing corresponding to the concurrent event signals is executed in order of priority, or requests for ordering or starting the processing are issued in order of priority.

First claim

What is claimed is:

1. A data processing apparatus, comprising:
a plurality of circuit modules that can generate event signals; and
a controller that controls processing corresponding to the generated event signals when the event signals are generated from the circuit modules,
wherein each of the circuit modules includes a concurrent flag that is set to a set state of a logical high level when generating a plurality of given event signals, different in priority of the processing, at the same time, and otherwise set to logical low level, and
wherein the controller refers to the concurrent flag of the circuit module of a request source when the circuit module generates the given event signals, and controls processing corresponding to a given event signal and processing corresponding to another event signal generated together with the given event signal to be set in order of priority when the concurrent flag is in the set state of the logical high level.

2. The data processing apparatus according to claim 1 , wherein when an event signal lower in priority among the plurality of event signals, the controller determines whether the concurrent event signals are generated, or not, with reference to the concurrent flag.

3. The data processing apparatus according to claim 1 , wherein when the controller determines that the event signals are generated at a same time, processing corresponding to the concurrent event signals is executed in order of priority, or requests for ordering or starting the processing are issued in order of priority, and
wherein the controller determines which is the processing corresponding to the concurrent event signals with reference to a processing request flag indicating that a processing request has been issued for each of the event signals.

4. A data processing apparatus, comprising:
a central processing unit that executes an instruction;
a plurality of circuit modules that can generate event signals; and
an interrupt controller that receives processing requests corresponding to the event signals generated from the circuit modules, mediates the processing requests that compete the reception according to a processing order corresponding to an interrupt priority, and requests the central processing unit to conduct the interrupt processing corresponding to the received processing request,
wherein the circuit modules each includes a concurrent flag, and changes the concurrent flag from a first state to a second state when generating a plurality of event signals, different in the interrupt priority, at the same time,
wherein, when receiving a request for given interrupt processing from the interrupt controller, the central processing unit refers to the concurrent flag of the circuit module pertaining to an interrupt factor of the request, executes the given interrupt processing corresponding to a given interrupt signal and interrupt processing corresponding to another event signal generated together with the given event signal in order of priority when the concurrent flag is in the second state, and
wherein the central processing unit sets the concurrent flag to the first state after referring to the concurrent flag.

5. The data processing apparatus according to claim 2 ,
wherein the interrupt controller has a processing request flag indicative of whether the processing request is present, or not, for each of the event signals, and
wherein the central processing unit determines whether the interrupt processing corresponding to the concurrent event signals is unprocessed, or not, with reference to the processing request flag, and clears the corresponding processing request flag in a no-request state after the interrupt processing is completed.

6. The data processing apparatus according to claim 2 ,
wherein the interrupt controller can inhibit multiple interrupt.

7. The data processing apparatus according to claim 2 ,
wherein the circuit modules and the interrupt controller operate in synchronization with different clock signals.

8. The data processing apparatus according to claim 2 ,
wherein the interrupt controller requests the interrupt processing by the interrupt signal and interrupt factor information responsive to the event signal.

9. A data processing apparatus, comprising:
a central processing unit that executes an instruction;
a plurality of circuit modules that can generate event signals; and
an interrupt controller that receives processing requests corresponding to the event signals generated from the circuit modules, mediates the processing requests that compete the reception according to a processing order corresponding to an interrupt priority, and requests the central processing unit to conduct the interrupt processing corresponding to the received processing request,
wherein the circuit modules each includes a concurrent flag, and changes the concurrent flag from a first state to a second state when generating a plurality of event signals, different in the interrupt priority, at the same time,
wherein, when receiving a processing request corresponding to a given event signal from the circuit module, the interrupt controller refers to the concurrent flag of the circuit module pertaining to a requested processing factor, requests interrupt processing corresponding to the given processing request, and interrupt processing corresponding to a processing request pertaining to another event signal generated together with the given event signal in order of priority, and
wherein the interrupt controller sets the concurrent flag to the first state after referring to the concurrent flag.

10. The data processing apparatus according to claim 9 ,
wherein the interrupt controller has a processing request flag indicative of whether the processing request is present, or not, for each of the event signals,
wherein the interrupt controller determines whether the interrupt processing corresponding to the concurrent event signals is unprocessed, or not, with reference to the processing request flag, and
wherein the central processing unit clears the corresponding processing request flag in a no-request state after the interrupt processing is completed.

11. The data processing apparatus according to claim 9 ,
wherein the interrupt controller can inhibit multiple interrupt.

12. The data processing apparatus according to claim 9 ,
wherein the circuit modules and the interrupt controller operate in synchronization with different clock signals.

13. The data processing apparatus according to claim 9 ,
wherein the interrupt controller requests the interrupt processing by the interrupt signal and interrupt factor information responsive to the event signal.

14. A data processing apparatus, comprising:
a central processing unit that executes an instruction;
a plurality of circuit modules that can generate event signals; and
an event link controller that receives the event signals generated from the circuit modules, mediates the event signals that compete the reception according to a processing order corresponding to a start priority, and can output a start control signal of operation to the circuit modules according to the received event signals,
wherein the circuit modules each includes a concurrent flag, and changes the concurrent flag from a first state to a second state when generating a plurality of event signals, different in the start priority, at the same time,
wherein the event link controller has a rewritable storage circuit, and the storage circuit is used for storage of event control information for specifying a start control signal to be output in response to the event signals,
wh

Assignees

• Renesas Electronics Corp

Inventors

• Nakashima Kenichi

Classifications

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F13/26 Primary

  with priority control · CPC title