Direct ring 3 submission of processing jobs to adjunct processors

Patent metadata

Field	Value
Publication number	US-9678795-B2
Application number	US-201113993089-A
Country	US
Kind code	B2
Filing date	Dec 30, 2011
Priority date	Dec 30, 2011
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

Transitions to ring 0, each time an application wants to use an adjunct processor, are avoided, saving central processor operating cycles and improving efficiency. Instead, initially each application is registered and setup to use adjunct processor resources in ring 3.

First claim

What is claimed is:

1. A method comprising:
enabling processor having a ring 3 to ring 0 resource to be used by an application running on a central processing unit repeatedly using only one transition of the central processing unit from ring 3, wherein a ring 3 to ring 0 resource is a resource that requires a transition from ring 3 to ring 0; and
avoiding a transition from ring 3 to ring 0 when the processor's ring 3 to ring 0 resource is used repeatedly by the central processing unit;
enabling the application to register to use an adjunct processor that is a ring 3 to ring 0 resource;
registering the application using a ring 3 to ring 0 transition and then enabling the application to use that resource thereafter without another ring 3 to ring 0 transition.

2. The method of claim 1 including establishing a region in virtual memory to indicate when an application wants to use the resource.

3. The method of claim 2 including enabling the adjunct processor to detect a write to that region.

4. The method of claim 3 including enabling the adjunct processor to schedule a job in response to detecting the write.

5. The method of claim 2 including mapping the adjunct processor to said region using a process address space.

6. The method of claim 2 including establishing said region as a write back page.

7. The method of claim 6 including assigning a line of said page and monitoring said line for a write including a request for an adjunct processor resource.

8. The method of claim 1 including providing a ring 0 driver to set up an identifier to identify said application.

9. A non-transitory computer readable medium storing instructions to enable a processor to:
enable processor having a ring 3 to ring 0 resource to be used by an application running on a central processing unit repeatedly using only one transition of the central processing unit from ring 3, wherein a ring 3 to ring 0 resource is a resource that requires a transition from ring 3 to ring 0; and
avoid a transition from ring 3 to ring 0 when the processor's ring 3 to ring 0 resource is used repeatedly by the central processing unit;
storing instructions to enable the application to register to use an adjunct processor that is a ring 3 to ring 0 resource;
storing instructions to register the application using a ring 3 to ring 0 transition and then enable the application to use that resource thereafter without another ring 3 to ring 0 transition.

10. The medium of claim 9 further storing instructions to establish a region in virtual memory to indicate when an application wants to use the resource.

11. The medium of claim 10 further storing instructions to enable the adjunct processor to detect a write to that region.

12. The medium of claim 11 further storing instructions to enable the adjunct processor to schedule a job in response to detecting the write.

13. The medium of claim 10 further storing instructions to map the adjunct processor to said region using a process address space.

14. The medium of claim 10 further storing instructions to establish said region as a write back page.

15. The medium of claim 14 further storing instructions to assign a line of said page and monitor said line for a write including a request for an adjunct processor resource.

16. The medium of claim 9 further storing instructions to provide a ring 0 driver to set up an identifier to identify said application.

17. An apparatus comprising:
a processor having a resource, and a central processing unit, coupled to said processor, said unit to enable an application running on the central processing unit to be used by an adjunct processor resource repeatedly using only one transition of the central processing unit from ring 3, wherein a ring 3 to ring 0 resource is a resource that requires a transition from ring 3 to ring 0, and avoid a transition from ring 3 to ring 0 when the processor's ring 3 to ring 0 resource is used repeatedly by the central processing unit;
said unit to enable the application to register to use the adjunct processor that is a ring 3 to ring 0 resource;
said unit to register the application using a ring 3 to ring 0 transition and then enable the application to use that resource thereafter without another ring 3 to ring 0 transition.

18. The apparatus of claim 17 , said unit to establish a region in virtual memory to indicate when an application wants to use the resource.

19. The apparatus of claim 18 , the adjunct processor to detect a write to that region.

20. The apparatus of claim 19 , the adjunct processor to schedule a job in response to detecting the write.

21. The apparatus of claim 17 including a ring 0 driver executed by said unit to set up an identifier to identify said application.

22. The apparatus of claim 18 , the adjunct processor to map to said region using a process address space.

23. The apparatus of claim 18 , said unit to establish said region as a write back page.

24. The apparatus of claim 23 , said unit to assign a line of said page and monitor said line for a write including a request for an adjunct processor resource.

Assignees

• Koker Altug
• Navale Aditya
• Vembu Balaji
• Ramadoss Murali
• Intel Corp

Inventors

• Koker Altug
• Navale Aditya
• Vembu Balaji
• Ramadoss Murali

Classifications

• G06F9/50 Primary

  Allocation of resources, e.g. of the central processing unit [CPU] · CPC title

• G06F15/167

  using a common memory, e.g. mailbox · CPC title

• G06F9/545

  where tasks reside in different layers, e.g. user- and kernel-space · CPC title

• G06F9/4812 Primary

  by interrupt, e.g. masked · CPC title

• G06F12/1491

  in a hierarchical protection system, e.g. privilege levels, memory rings · CPC title