Methods and systems for calibration of voltage regulator systems with multiple types of power stages

Patent metadata

Field	Value
Publication number	US-9678555-B2
Application number	US-201414470217-A
Country	US
Kind code	B2
Filing date	Aug 27, 2014
Priority date	Jun 19, 2014
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

Methods and systems are disclosed that may be employed to enable multi-phase voltage regulator (VR) system calibration during the development phase of a multi-phase VR system so as to meet defined accuracy targets and, in one example, to avoid the need for system level calibration in a production environment. The disclosed systems and methods may be further implemented to enable use of multiple sources for and types of integrated power stages (IPstages) in a common multi-phase VR system configuration while still achieving the required current sense accuracy, thus reducing or substantially eliminating continuity of supply (COS) concerns.

First claim

What is claimed is:

1. A voltage regulator (VR) system, comprising:
at least one integrated power stage (IPstage) comprising a power output, current sense circuitry configured to sense output current from the at least one IPstage, and an IPstage identification (ID) recognition module having a power device identification signal output that is indicative of the identity of the at least one IPstage;
at least one processing device configured as a VR system controller coupled to control operation of the at least one IPstage, the at least one processing device also being coupled to receive a current sense output signal from the IPstage current sense circuitry and to receive the power device identification signal output from the at least one IPstage; and
non-volatile memory (NVM) coupled to the VR system controller, the memory storing different IPstage operating parameter values corresponding to multiple different types of IPstages that include the at least one IPstage;
where the at least one processing device is configured to:
receive the power device identification signal output from the at least one IPstage,
determine the identity of the at least one IPstage based on the received power device identification signal,
retrieve IPstage operating parameter values that correspond to the identified IPstage from the NVM, and
use the retrieved IPstage operating parameter values together with the current sense output signal from the IPstage current sense circuitry to determine IPstage output current while controlling the at least one IPstage to provide power to the VR system power output.

2. The system of claim 1 , where the IPstage operating parameter values that correspond to the identified IPstage are stored on the NVM together with multiple sets of IPstage operating parameters for different types of IPstages in a single configuration file, each of the multiple different types of IPstages having different electrical characteristics and current sense circuitry accuracy; and where the processing device is configured to identify and retrieve the IPstage operating parameter values that correspond to an identified type of IPstage from the single configuration file.

3. The system of claim 2 , where the processing device is further configured to determine if the identified type of IPstage has a manufacturing date and/or lot code that matches a manufacturing date and/or lot code assigned to the retrieved IPstage operating parameter values; and to update the retrieved IPstage operating parameter values by tuning the retrieved IPstage operating parameter values prior to determining the IPstage output current if the manufacturing date and/or lot code of the identified type of IPstage does not match the manufacturing date and/or lot code assigned to the retrieved IPstage operating parameter values.

4. The system of claim 1 , where the VR system comprises multiple different IPstages that correspond to the multiple different types of IPstages, each of the multiple different types of IPstages having different electrical characteristics and current sense circuitry accuracy; and where the processing device is configured to:
separately receive the power device identification signal output from each of the different types of IPstages of the VR system;
determine the identity of each of the different IPstages based on the received power device identification signal;
retrieve IPstage operating parameter values that correspond to each of the identified different IPstages from the NVM; and
use the retrieved IPstage operating parameter values for each one of the different types of IPstages together with the current sense output signal from the IPstage current sense circuitry of each corresponding one of the different types of IPstages to determine the IPstage output current from the IPstage current sense circuitry of each corresponding one of the different types of IPstages while controlling each corresponding one of different IPstages to provide power to the VR system power output.

5. The system of claim 4 , where IPstage operating parameter values are stored in multiple different configuration files on the NVM, each of the multiple different configuration files containing IPstage operating parameters for a different given type of IPstage device from a particular vendor or supplier source stored on the NVM; and where the processing device is configured to identify and select a configuration file that corresponds to the vendor or supplier source of the identified type of IPstage, and to retrieve the IPstage operating parameter values from the selected configuration file that correspond to an identified type of IPstage from the single configuration file.

6. The system of claim 4 , where the processing device is further configured to determine if the identified type of IPstage has a manufacturing date and/or lot code that matches a manufacturing date and/or lot code assigned to retrieved IPstage operating parameter values; and to update IPstage operating parameter values stored in the selected configuration file on the NVM by tuning retrieved IPstage operating parameter values prior to determining the IPstage output current if the manufacturing date and/or lot code of the identified type of IPstage does not match the manufacturing date and/or lot code assigned to retrieved IPstage operating parameter values, and updating the selected configuration file on the NVM by storing the tuned IPstage operating parameters.

7. The system of claim 1 , where the IPstage operating parameters comprises at least one of current sense gain, current sense offset, current sense temperature compensation, or a combination thereof.

8. A method of operating a voltage regulator (VR) system that includes at least one processing device, comprising:
using the at least one processing device to control operation of at least one integrated power stage (IPstage) of the VR system that includes a power output, current sense circuitry, and an IPstage identification (ID) recognition module having a power device identification signal output that is indicative of the identity of the at least one IPstage;
receiving a current sense output signal in the at least one processing device from the IPstage current sense circuitry and receiving the power device identification signal output in the at least one processing device from the at least one IPstage; and
determining the identity of the at least one IPstage based on the received power device identification signal,
retrieving IPstage operating parameter values that correspond to the identified IPstage from non-volatile memory (NVM) coupled to a VR system controller, the memory storing different IPstage operating parameter values corresponding to multiple different types of IPstages that include the at least one IPstage, and
using the retrieved IPstage operating parameter values together with the current sense output signal from the IPstage current sense circuitry to determine a IPstage output current while controlling the at least one IPstage to provide power to the VR system power output.

9. The method of claim 8 , where the IPstage operating parameter values that correspond to the identified IPstage are stored on the NVM together with multiple sets of IPstage operating parameters for different types of IPstages in a single configuration file, each of the different types of IPstages having different electrical characteristics and current sense circuitry accuracy; and where the method further comprises using the at least one processing device to identify and retrieve IPstage operating parameter values that correspond to an identified type of IPstage from the single configuration file.

10. The method of claim 8 , further comprising using the a

Assignees

• Luo Shiguo
• Zhang Kejiu
• Li Hang
• Breen John J
• Dell Products Lp

Inventors

• Luo Shiguo
• Zhang Kejiu
• Li Hang
• Breen John J

Classifications

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title