Apparatuses and methods for power regulation based on input power

Patent metadata

Field	Value
Publication number	US-9678524-B2
Application number	US-201514866152-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Sep 25, 2015
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

Apparatuses and methods for power regulation based on input power using circuitry are disclosed herein. An example apparatus may include a reference circuit configured to receive a first voltage and a second voltage and to provide an output reference voltage at an output node having a value equal to the second voltage subtracted from the first voltage. The reference circuit may be configured to mirror a current of a first circuit coupled between the second voltage and a reference voltage through a second circuit coupled between the first voltage and the output node. The example apparatus may further include a power circuit configured to provide a third voltage based on the output reference voltage. The third voltage may have a value that is equal to the output reference voltage.

First claim

What is claimed is:

1. An apparatus, comprising:
a power regulator circuit configured to receive a first voltage and to generate a second voltage using the first voltage, wherein the second voltage is less than the first voltage, wherein the power regulator circuit is further configured to generate a third voltage equal to the second voltage subtracted from the first voltage using current mirroring; and
an output buffer configured to provide an output signal based on an input signal, wherein a voltage of the output signal varies between the first voltage and a reference voltage provided by a reference source, wherein a first transistor of the output buffer is configured to be driven using the first voltage or the third voltage based on the input data and a second transistor of the output buffer is configured to be driven using one of the second voltage or the reference voltage based on the input data.

2. The apparatus of claim 1 , wherein the power regulator circuit comprises:
a first voltage regulator configured to provide the second voltage based on the first voltage; and
a second voltage regulator configured to provide the third voltage based on the first voltage and the second voltage.

3. The apparatus of claim 2 , wherein the first voltage regulator comprises a direct current to direct current voltage regulator.

4. The apparatus of claim 2 , wherein the second voltage regulator comprises:
a reference circuit configured to provide an output reference voltage that is equal to the difference of the first and second voltages; and
a power circuit configured to provide the third voltage based on the output reference voltage.

5. The apparatus of claim 4 , wherein the reference circuit comprises:
a first circuit coupled between an output of the first voltage regulator and a reference source configured to provide the reference voltage; and
a second circuit coupled between an output node and a first source configured to provide the first voltage, wherein the first circuit is matched with the second circuit,
wherein the reference circuit is further configured to mirror a current of the first circuit through the second circuit.

6. The apparatus of claim 5 , wherein the first circuit includes a first transistor coupled in series with a second transistor between the output of the first voltage regulator and the reference source, wherein the gate of the second transistor is coupled to the reference source and the gate of the first transistor is coupled to the drain of the first transistor, wherein the second circuit includes a third transistor coupled in series with a fourth transistor between the first source and the output node, wherein the gate of the fourth transistor is coupled to the output node and the gate of the first transistor is coupled to the drain of the third transistor.

7. The apparatus of claim 6 , wherein the reference circuit further comprises a fifth transistor including a source coupled to output of the first voltage regulator and a gate coupled to the gate of the first transistor to mirror the current through the first transistor.

8. The apparatus of claim 7 , wherein the reference circuit further comprises a sixth transistor including a source coupled to the first source and a gate coupled to the gate of the third transistor to mirror the current through the third transistor.

9. The apparatus of claim 8 , wherein the reference circuit further comprises:
a seventh transistor including a drain coupled to a drain of the sixth transistor and including a source coupled to the reference source, wherein a gate of the seventh transistor is coupled to the drain of the seventh transistor; and
an eighth transistor including a drain coupled the drain of the fifth transistor and including a source coupled to the reference source, a gate of the eighth transistor coupled to the gate of the seventh transistor to mirror the current through the seventh transistor.

10. The apparatus of claim 9 , wherein the reference circuit further comprises a ninth transistor including a drain coupled to the output node and including a source coupled to the reference source, wherein a gate of the ninth transistor is coupled to the drain of the fifth transistor to provide feedback to the second circuit.

11. The apparatus of claim 10 , wherein the reference circuit further comprises:
a tenth transistor coupled between the output node and the ninth transistor to form a first cascode driver with the ninth transistor, wherein a gate of the tenth transistor is coupled to the output of the first voltage regulator; and
an eleventh transistor coupled between the drain of the sixth transistor and a drain of the seventh transistor to form a second cascode driver with the sixth transistor, wherein a gate of the eleventh transistor is coupled to the output node.

12. The apparatus of claim 10 , wherein the reference circuit further comprises:
a first capacitor coupled between the first source and the output node to form a tank circuit; and
a second capacitor coupled between the output node and the drain of the fifth transistor to provide a stable frequency response.

13. The apparatus of claim 1 , wherein each transistor of the power regulator circuit and each transistor of the output buffer is configured to operate at a voltage differential that is equal to or less than the second voltage.

14. An apparatus comprising:
a reference circuit configured to receive a first voltage and a second voltage and to provide an output reference voltage at an output node, the output reference voltage having a value equal to the second voltage subtracted from the first voltage; and
a power circuit comprising an output node configured to provide an output voltage based on the output reference voltage; wherein the power circuit comprises:
a first circuit coupled between a first voltage source and the output node of the reference circuit, wherein the first circuit comprises a first transistor having a source coupled to the first voltage source and a gate coupled to the output node of the reference circuit, the first circuit further comprising a second transistor having a drain coupled to a drain of the first transistor and a source coupled to the output node of the reference circuit, wherein a gate of the second transistor is coupled to the drain of the second transistor; and
a second circuit coupled between the first voltage source and an output node of the power circuit, wherein the second circuit comprises a third transistor having a source coupled to the first voltage source and a gate coupled to the output node of the reference circuit, the second circuit further comprising a fourth transistor having a drain coupled to a drain of the third transistor and a source coupled to the output node of the power circuit, wherein a gate of the second transistor is coupled to the drain of the second transistor.

15. The apparatus of claim 14 , wherein the power circuit further comprises:
a voltage-to-current converter comprising a fifth transistor comprising a drain coupled to the first voltage source and a gate coupled to the drain of the fourth transistor and further comprising a sixth transistor having a source coupled to the source of the fifth transistor and a gate coupled to the output node of the reference circuit; and
a current multiplier comprising a seventh transistor having a drain coupled to a drain of the sixth transistor, a source coupled to a reference voltage source, and a gate coupled to the drain of the seventh transistor, the current multiplier further comprising an eighth transistor having a drain coupled to the output node of the power cir

Assignees

• Micron Technology Inc

Inventors

• Pisasale Michelangelo
• Gaibotti Maurizio Giovanni

Classifications

• G05F3/26 Primary

  Current mirrors · CPC title

• H03K19/003

  Modifications for increasing the reliability {for protection} · CPC title

• H03K17/30

  Modifications for providing a predetermined threshold before switching (shaping pulses by thresholding H03K5/08) · CPC title

• H03K17/10

  Modifications for increasing the maximum permissible switched voltage · CPC title

• H03K17/12

  Modifications for increasing the maximum permissible switched current · CPC title