Diagnosis of integrated driver circuits

Patent metadata

Field	Value
Publication number	US-9676357-B2
Application number	US-81605310-A
Country	US
Kind code	B2
Filing date	Jun 15, 2010
Priority date	Jun 15, 2010
Publication date	Jun 13, 2017
Grant date	Jun 13, 2017

Abstract

A circuit arrangement includes a controller and an integrated driver arrangement coupled to the controller. The integrated driver circuit includes a driver unit having at least one operation parameter, and a diagnostic unit coupled to the driver unit. The diagnostic unit is adapted to retrieve the at least one operation parameter from the driver unit, and is coupled to the controller.

First claim

What is claimed is:

1. A circuit arrangement comprising:
a controller and an integrated driver circuit coupled to a communication port of the controller, wherein the integrated driver circuit comprises
an electronic output driver unit comprising a first transistor configured to drive a load, wherein the electronic output driver unit is configured to determine at least one operation parameter indicating whether the electronic output driver unit is in a fault state, and
a diagnostic unit coupled to the electronic output driver unit and coupled to an interrupt port of the controller, wherein the interrupt port is different from the communication port,
wherein the diagnostic unit is adapted to retrieve the at least one operation parameter from the electronic output driver unit, evaluate the at least one operation parameter in order to obtain a diagnostic result, store the diagnostic result in a storage memory, and send an interrupt signal to the controller via the interrupt port upon detection of the fault state of the output driver unit, and
wherein the controller, via the communication port, is configured to read out the diagnostic result stored in the memory upon receipt of the interrupt signal from the diagnostic unit.

2. The circuit arrangement of claim 1 , further comprising a storage memory coupled to the diagnostic unit and the controller.

3. The circuit arrangement of claim 2 , wherein the diagnostic unit is adapted to store the at least one operation parameter in the storage memory.

4. The circuit arrangement of claim 2 , wherein the diagnostic unit is adapted to evaluate the at least one operation parameter in order to obtain a diagnostic result, and is adapted to store the diagnostic result in the storage memory.

5. The circuit arrangement of claim 1 , further comprising a communication channel between the controller and the integrated driver circuit.

6. The circuit arrangement of claim 5 , wherein the integrated driver circuit further comprises an internal bus, wherein the diagnostic unit, the electronic output driver unit, and the communication channel are coupled to the internal bus.

7. The circuit arrangement of claim 5 , further comprising an interrupt channel between the diagnostic unit and the controller.

8. The circuit arrangement of claim 2 , further comprising an interrupt signal channel between the diagnostic unit and the controller.

9. The circuit arrangement of claim 1 , wherein the controller is a microcontroller.

10. The circuit arrangement of claim 1 , wherein the controller and the integrated driver circuit are integrated in at least two separate integrated circuits.

11. The circuit arrangement of claim 1 , further comprising a sensor coupled to the controller.

12. The circuit arrangement of claim 1 , wherein the electronic output driver unit comprises:
an output stage having at the least one operation parameter;
a measurement unit coupled to the output stage and adapted to measure the at least one operation parameter; and
an interface circuit coupled to the diagnostic unit and the measurement unit.

13. The circuit arrangement of claim 12 , further comprising a driver stage coupled between the interface circuit and the output stage.

14. The circuit arrangement of claim 13 , wherein the measurement unit is coupled to the driver stage.

15. The circuit arrangement of claim 12 , wherein the output stage comprises:
the first transistor having a control terminal and a load path, and having its load path coupled between a first supply terminal and a first load terminal of the electronic output driver unit; and
a second transistor having a control terminal and a load path, and having its load path coupled between a second supply terminal and a second load terminal of the electronic output driver unit.

16. The circuit arrangement of claim 15 , wherein the measurement unit is adapted to measure an electrical resistance between the first and second load terminals as an operation parameter.

17. The circuit arrangement of claim 12 , wherein the electronic output driver unit further comprises a fault injection that can be activated and deactivated, and that is coupled to the interface circuit and to the measurement unit.

18. The circuit arrangement of claim 3 , wherein the diagnostic unit is coupled to the controller via an interrupt channel, and wherein the controller is configured to poll the at least one operation parameter from the storage memory via a communication channel different from the interrupt channel.

19. The circuit arrangement of claim 18 , wherein the controller is configured to poll the at least one operation parameter from the storage memory upon receiving an interrupt signal from the diagnostic unit via the interrupt channel.

20. The circuit arrangement of claim 18 , wherein the output driver unit, the diagnostic unit, and the storage memory are coupled to an internal bus, wherein the internal bus is coupled to the communication channel.

21. The circuit arrangement of claim 20 , wherein the internal bus is coupled to the communication channel via an interface circuit.

22. The circuit arrangement of claim 1 , wherein the diagnostic unit is adapted to regularly poll the at least one operation parameter from the electronic output driver unit and to evaluate the retrieved operation parameter.

23. A circuit arrangement comprising:
a controller and an integrated driver circuit coupled to a communication port of the controller, wherein the integrated driver circuit comprises
an electronic output driver unit comprising a first load terminal and a second load terminal,
an output stage disposed in the electronic output driver unit and comprising a first transistor configured to drive a load between the first and the second load terminals,
a measurement circuit disposed in the electronic output driver unit and coupled to the output stage, the measurement circuit configured to measure at least one operation parameter at the first load terminal and/or the second load terminal, wherein the at least one operation parameter is configured to indicate whether the electronic output driver unit is in a fault state, and
a diagnostic unit coupled to the electronic output driver unit and coupled to an interrupt port of the controller, wherein the interrupt port is different from the communication port,
wherein the diagnostic unit is adapted to retrieve the at least one operation parameter from the electronic output driver unit, evaluate the at least one operation parameter in order to obtain a diagnostic result, store the diagnostic result in a storage memory, and send an interrupt signal to the controller via the interrupt port upon detection of the fault state of the output driver unit, and
wherein the controller, via the communication port, is configured to read out the diagnostic result stored in the memory upon receipt of the interrupt signal from the diagnostic unit.

24. The circuit arrangement of claim 23 , wherein the output stage comprises:
the first transistor having a control terminal and a load path, and having its load path coupled between a first supply terminal and the first load terminal; and
a second transistor having a control terminal and a load path, and having its load path coupled between a second supply terminal and the second load terminal.

25. The circuit arrangement of claim 23 , wherein the measurement circuit is configured to measure a voltage drop across the fi

Assignees

• Dittfeld Timo
• Scherr Wolfgang
• Infineon Technologies Ag

Inventors

• Dittfeld Timo
• Scherr Wolfgang

Classifications

• G01R31/007

  using microprocessors or computers · CPC title

• B60R21/0173 Primary

  Diagnostic or recording means therefor · CPC title