Power multiplexing with flip-flops

Patent metadata

Field	Value
Publication number	US-9673787-B2
Application number	US-201514861503-A
Country	US
Kind code	B2
Filing date	Sep 22, 2015
Priority date	Sep 22, 2015
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Data retention circuitry, such as at least one integrated circuit (IC), is disclosed herein for power multiplexing with flip-flops having a retention feature. In an example aspect, an IC includes a first power rail and a second power rail. The IC further includes a flip-flop and power multiplexing circuitry. The flip flop includes a master portion and a slave portion. The master portion is coupled to the first power rail for a regular operational mode and for a retention operational mode. The power multiplexing circuitry is configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode.

First claim

What is claimed is:

1. Data retention circuitry comprising:
a first power rail;
a second power rail;
a flip-flop including a master portion and a slave portion, the master portion coupled to the first power rail for a regular operational mode and for a retention operational mode, the flip-flop further including isolation circuitry configured to isolate the master portion from the slave portion for the retention operational mode;
power multiplexing circuitry configured to couple the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode; and
power collapse circuitry including clamping circuitry configured to clamp a clock signal responsive to an active state of a retention signal to produce a controlled clock signal;
wherein the power collapse circuitry is configured to establish a retention state of the isolation circuitry to prevent the master portion from changing slave data stored by the slave portion for the retention operational mode and to provide the controlled clock signal to the isolation circuitry to establish the retention state of the isolation circuitry to prevent the master portion from changing the slave data stored by the slave portion for the retention operational mode.

2. The data retention circuitry of claim 1 , wherein:
the master portion is configured to experience a power collapse for the retention operational mode; and
the slave portion is configured to retain the slave data stored by the slave portion for the retention operational mode.

3. The data retention circuitry of claim 1 , wherein:
the first power rail comprises a collapsible power rail; and
the power collapse circuitry is configured to remove power from the collapsible power rail for the retention operational mode.

4. The data retention circuitry of claim 3 , wherein:
the collapsible power rail is coupled to a switched-mode power supply; and
the power collapse circuitry is further configured to turn off the switched-mode power supply for the retention operational mode.

5. The data retention circuitry of claim 1 , wherein the power multiplexing circuitry is further configured to:
decouple the slave portion from the first power rail during a power-down transitional period that occurs after the regular operational mode and before the retention operational mode; and
couple the slave portion to the second power rail during the power-down transitional period.

6. The data retention circuitry of claim 5 ,
wherein the power collapse circuitry is configured to remove power from the first power rail after the slave portion is decoupled from the first power rail and coupled to the second power rail for the retention operational mode.

7. The data retention circuitry of claim 1 , wherein the power multiplexing circuitry is further configured to:
decouple the slave portion from the second power rail during a power-up transitional period that occurs after the retention operational mode and before the regular operational mode; and
couple the slave portion to the first power rail during the power-up transitional period.

8. The data retention circuitry of claim 1 , wherein the data retention circuitry is configured to:
hold the first power rail at a first voltage;
hold the second power rail at a second voltage; and
for the retention operational mode, maintain the second voltage at a level that is higher than a level of the first voltage and that is sufficient to meet a retention voltage level of the slave portion.

9. The data retention circuitry of claim 1 , further comprising:
a first power supply coupled to the first power rail, the first power supply configured to provide power to the first power rail;
a second power supply coupled to the second power rail, the second power supply configured to provide power to the second power rail, wherein the power collapse circuitry is configured to turn off the first power supply for the retention operational mode.

10. The data retention circuitry of claim 1 , further comprising volatile memory coupled to the second power rail.

11. The data retention circuitry of claim 10 , wherein:
the second power rail is coupled to a switched-mode power supply, wherein the power collapse circuitry is configured to decrease an output voltage of the switched-mode power supply from a regular voltage level to a retention voltage level for the retention operational mode.

12. The data retention circuitry of claim 1 , wherein:
the power multiplexing circuitry comprises:
a first switch coupled between the slave portion of the flip-flop and the first power rail; and
a second switch coupled between the slave portion of the flip-flop and the second power rail; and

the power multiplexing circuitry is further configured to close the first switch and open the second switch for the regular operational mode and to open the first switch and close the second switch for the retention operational mode.

13. Data retention circuitry comprising:
a first power rail;
a second power rail;
a flip-flop including a master portion and a slave portion, the master portion coupled to the first power rail for both a regular operational mode and a retention operational mode, the slave portion configured to retain slave data if the master portion experiences a power collapse for the retention operational mode, the flip flop further including isolation circuitry configured to isolate the master portion from the slave portion for the retention operational mode;
means for power multiplexing the slave portion to the first power rail for the regular operational mode and to the second power rail for the retention operational mode; and
power collapse circuitry including means for clamping a clock signal responsive to an active state of a retention signal to produce a controlled clock signal;
wherein the power collapse circuitry is configured to establish a retention state of the isolation circuitry to prevent the master portion from changing the slave data stored by the slave portion for the retention operational mode and to provide the controlled clock signal to the isolation circuitry to establish the retention state of the isolation circuitry to prevent the master portion from changing the slave data stored by the slave portion for the retention operational mode.

14. The data retention circuitry of claim 13 , wherein the means for power multiplexing comprises means for switching between coupling the slave portion to the first power rail and coupling the slave portion to the second power rail.

15. The data retention circuitry of claim 13 , wherein the flip-flop further includes means for isolating the slave portion from the master portion for the retention operational mode.

16. The data retention circuitry of claim 13 , further comprising means for removing power from the first power rail for the retention operational mode.

17. The data retention circuitry of claim 13 , wherein:
the data retention circuitry further comprises:
a first power supply coupled to the first power rail; and
a second power supply coupled to the second power rail;

the means for power multiplexing comprises a means for switching between coupling the slave portion to the first power rail and coupling the slave portion to the second power rail, the means for switching configured to operate during a transitional period that occurs between the regular operational mode and the retention operational mode;
the master portion of the flip-flop is configured to receive power supplied by the first power supply for the regular o

Assignees

• Qualcomm Inc

Inventors

• Cao Lipeng
• Gemar Jeffrey
• Vilangudipitchai Ramaprasath

Classifications

• H03K3/0372 Primary

  of the primary-secondary type · CPC title

• H03K3/356008 Primary

  ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00) · CPC title

• H03K3/3562

  of the primary-secondary type · CPC title

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title