Apparatus and methods for high voltage variable capacitor arrays with body biasing resistors

Patent metadata

Field	Value
Publication number	US-9673774-B2
Application number	US-201514705381-A
Country	US
Kind code	B2
Filing date	May 6, 2015
Priority date	Dec 3, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells.

First claim

What is claimed is:

1. An integrated circuit comprising:
a variable capacitor array including at least three variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output, wherein each of the at least three variable capacitor cells includes:
two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors electrically connected in series between the RF input and the RF output, wherein a first pair of the two or more pairs of anti-series MOS capacitors includes a first MOS capacitor and a second MOS capacitor electrically connected in anti-series, and wherein a second pair of the two or more pairs of anti-series MOS capacitors includes a third MOS capacitor and a fourth MOS capacitor electrically connected in anti-series; and
a plurality of body biasing resistors configured to bias a plurality of bodies of the two or more pairs of anti-series MOS capacitors with a body bias voltage; and

a bias voltage generation circuit configured to bias at least a first variable capacitor cell of the at least three variable capacitor cells to control a capacitance of the variable capacitor array,
wherein the integrated circuit does not include any switches along a signal path between the RF input and the RF output through the variable capacitor array.

2. The integrated circuit of claim 1 , wherein the bias voltage generation circuit is further configured to generate the body bias voltage.

3. The integrated circuit of claim 1 , wherein the plurality of body biasing resistors of each of the at least three variable capacitor cells comprises:
a first body biasing resistor including a first end configured to receive the body bias voltage and a second end electrically connected to a body of the first MOS capacitor of each of the at least three variable capacitor cells;
a second body biasing resistor including a first end configured to receive the body bias voltage and a second end electrically connected to a body of the second MOS capacitor of each of the at least three variable capacitor cells;
a third body biasing resistor including a first end configured to receive the body bias voltage and a second end electrically connected to a body of the third MOS capacitor of each of the at least three variable capacitor cells; and
a fourth body biasing resistor including a first end configured to receive the body bias voltage and a second end electrically connected to a body of the fourth MOS capacitor of each of the at least three variable capacitor cells.

4. The integrated circuit of claim 3 , wherein the two or more pairs of anti-series MOS capacitors further comprises a third pair of anti-series MOS capacitors comprising a fifth MOS capacitor and a sixth MOS capacitor electrically connected in anti-series, wherein the plurality of body biasing resistors further comprises:
a fifth body biasing resistor including a first end configured to receive the body bias voltage and a second end electrically connected to a body of the fifth MOS capacitor; and
a sixth body biasing resistor including a first end configured to receive the body bias voltage and a second end electrically connected to a body of the sixth MOS capacitor.

5. The integrated circuit of claim 1 , wherein each of the plurality of body biasing resistors has a resistance in the range of 10 kΩ to 10,000 kΩ.

6. The integrated circuit of claim 1 , wherein the bias voltage generation circuit is configured to bias the first variable capacitor cell with a first bias voltage, wherein the bias voltage generation circuit is configured to control the first bias voltage to a voltage level selected from a discrete number of two or more bias voltage levels.

7. The integrated circuit of claim 6 , wherein the first MOS capacitor of each of the at least three variable capacitor cells and the second MOS capacitor of each of the at least three variable capacitor cells are electrically connected to one another at a first intermediate node of each of the at least three variable capacitor cells, wherein the third MOS capacitor of each of the at least three variable capacitor cells and the fourth MOS capacitor of each of the at least three variable capacitor cells are electrically connected to one another at a second intermediate node of each of the at least three variable capacitor cells, wherein the first variable capacitor cell further comprises:
a first control biasing resistor electrically connected between the first intermediate node of the first variable capacitor cell and the first bias voltage; and
a second control biasing resistor electrically connected between the second intermediate node of the first variable capacitor cell and the first bias voltage.

8. The integrated circuit of claim 1 , wherein a gate of the first MOS capacitor of each of the at least three variable capacitor cells is electrically connected to a gate of the second MOS capacitor of each of the at least three variable capacitor cells, and wherein a gate of the third MOS capacitor of each of the at least three variable capacitor cells is electrically connected to a gate of the fourth MOS capacitor of each of the at least three variable capacitor cells.

9. The integrated circuit of claim 1 , wherein a source and a drain of the first MOS capacitor of each of the at least three variable capacitor cells are electrically connected to a source and a drain of the second MOS capacitor of each of the at least three variable capacitor cells, and wherein a source and a drain of the third MOS capacitor of each of the at least three variable capacitor cells are electrically connected to a source and a drain of the fourth MOS capacitor of each of the at least three variable capacitor cells.

10. An apparatus comprising:
a radio frequency (RF) input;
an RF output;
at least three variable capacitor cells electrically connected in parallel between the RF input and the RF output, wherein each of the at least three variable capacitor cells includes:
two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors electrically connected in series between the RF input and the RF output, wherein a first pair of the two or more pairs of anti-series MOS capacitors includes a first MOS capacitor and a second MOS capacitor electrically connected in anti-series, and wherein a second pair of the two or more pairs of anti-series MOS capacitors includes a third MOS capacitor and a fourth MOS capacitor electrically connected in anti-series; and
a plurality of body biasing resistors configured to bias a plurality of bodies of the two or more pairs of anti-series MOS capacitors with a body bias voltage; and

a bias voltage generation circuit configured to generate a first bias voltage, wherein the bias voltage generation circuit is configured to bias the two or more pairs of anti-series MOS capacitors of at least one of the three variable capacitor cells with the first bias voltage to control a capacitance of the at least one of the three variable capacitor cells,
wherein each of the at least three variable capacitor cells does not include any switches along a signal path between the RF input and the RF output through the variable capacitor array.

11. The integrated circuit of claim 1 , wherein the integrated circuit is fabricated using a silicon on insulator (SOI) substrate.

12. The integrated circuit of claim 1 , wherein each of the at least three variable capacitor cells comprises at least three pairs of anti-series MOS capacitors electrically connected in series between the RF input and the RF output.

13. The integrated circuit of claim 1 , wherein the first MOS capacitor of each of the at least three variable c

Assignees

• Tdk Corp

Inventors

• Madan Anuj
• Gupta Dev V
• Lai Zhiguo

Classifications

• H03H7/0153

  Electrical filters; Controlling thereof · CPC title

• H03H7/17

  Structural details of sub-circuits of frequency selective networks · CPC title

• H03H5/12 Primary

  with at least one voltage- or current-dependent element · CPC title

• H03H1/02

  RC networks, e.g. filters · CPC title

• H03H2001/0014

  Capacitor filters, i.e. capacitors whose parasitic inductance is of relevance to consider it as filter · CPC title