Modified tunneling field effect transistors and fabrication methods

Patent metadata

Field	Value
Publication number	US-9673757-B2
Application number	US-201414156565-A
Country	US
Kind code	B2
Filing date	Jan 16, 2014
Priority date	Jan 16, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Tunneling field effect transistors and fabrication methods thereof are provided, which include: obtaining a gate structure disposed over a substrate structure; and providing a source region and a drain region within the substrate structure separated by a channel region, the channel region underlying, at least partially, the gate structure, and the providing including: modifying the source region to attain a narrowed source region bandgap; and modifying the drain region to attain a narrowed drain region bandgap, the narrowed source region bandgap and the narrowed drain region bandgap facilitating quantum tunneling of charge carriers from the source region or the drain region to the channel region. Devices including digital modulation circuits with one or more tunneling field effect transistor(s) are also provided.

First claim

What is claimed is:

1. A method comprising:
fabricating a tunneling field effect transistor, the fabricating comprising:
obtaining a gate disposed over a substrate structure;
providing a source region, the source region being one of an n-type and a p-type, and a drain region, the drain region being the other of an n-type and a p-type, within the substrate structure separated by a channel region, the channel underlying, at least partially, the gate, wherein each of the source region, drain region and channel region have a region bandgap defined by a region valence band and a region conduction band;
overlapping the source region with the gate to form a source region junction;
overlapping the drain region with the gate to form a drain region junction;

modifying the source region to attain a narrowed source region bandgap that is at least 60meV narrower than the channel region bandgap; and
modifying the drain region to attain a narrowed drain region bandgap that is at least 60meV narrower than the channel region bandgap, the narrowed source region bandgap and the narrowed drain region bandgap facilitating quantum tunneling of charge carriers between at least one of the region valence bands and at least one of the region conduction bands such that the charge carriers conduct from the source region or the drain region to the channel region;
applying a biased gate voltage to the gate such that, within the source region junction, the region valence and conduction bands are bent to enhance quantum tunneling of one of a hole type charge carrier and an electron type charge carrier; and
applying an oppositely biased gate voltage to the gate such that, within the drain region junction, the region valence and conduction bands are bent to enhance quantum tunneling of the other of a hole type charge carrier and an electron type charge carrier.

2. The method of claim 1 , wherein the overlapping comprises overlapping with the gate by substantially 10 nanometers.

3. The method of claim 1 , wherein the narrowed source region bandgap and the narrowed drain region bandgap are substantially equal bandgaps.

4. The method of claim 1 , wherein modifying the source region to attain the narrowed source region bandgap comprises adjusting at least one of the source region valence band or the source region conduction band, and modifying the drain region to attain the narrowed drain region bandgap comprises adjusting at least one of the drain region valence band or the drain region conduction band.

5. The method of claim 4 , wherein modifying the source region to attain the narrowed source region bandgap comprises adjusting both the source region valence band and the source region conduction band.

6. The method of claim 5 , wherein modifying the drain region to attain the narrowed drain region bandgap comprises adjusting both the drain region valence band and the drain region conduction band.

7. The method of claim 1 , wherein the source region of the substrate structure comprises a first region of carbon-doped silicon-germanium material, and the drain region of the substrate structure comprises a second region of carbon-doped silicon-germanium material, the carbon-doped silicon-germanium material providing the narrowed source region bandgap in the first region and the narrowed drain region bandgap in the second region.

8. The method of claim 1 , wherein modifying the source region to attain the narrowed source region bandgap comprises inducing a memorized stress in the source region of the substrate structure, and modifying the drain region to attain the narrowed drain region bandgap comprises inducing another memorized stress in the drain region of the substrate structure.

9. The method of claim 8 , wherein the memorized stress comprises a stacking fault in the source region of the substrate structure and the another memorized stress comprises another stacking fault in the drain region of the substrate structure.

10. The method of claim 1 , wherein modifying the source region and modifying the drain region comprise:
removing portions of the source region and the drain region to form a source cavity in the source region of the substrate structure and a drain cavity in the drain region of the substrate structure; and
providing a common material within the source cavity of the source region and the drain cavity of the drain region, wherein the common material has a common bandgap, the narrowed source region bandgap and the narrowed drain region bandgap equaling the common bandgap.

11. The method of claim 10 , wherein the common material comprises a carbon-doped silicon-germanium material.

12. The method of claim 10 , wherein modifying the source region and modifying the drain region of the substrate structure further comprise, after providing the common material within the source cavity and the drain cavity, implanting one of the source region or the drain region with an n-type implant to form n-type material and the other of the source region or the drain region with a p-type implant to form p-type material.

13. The method of claim 12 , wherein modifying the source region and modifying the drain region further comprise, after implanting, annealing the substrate structure, wherein the annealing facilitates attaining the narrowed source region bandgap and attaining the narrowed drain region bandgap.

14. The method of claim 12 , wherein the common material comprises silicon-germanium, the n-type implant comprises carbon and n-type dopants, and the p-type implant comprises carbon and p-type dopants.

Assignees

• Globalfoundries Inc

Inventors

• Liu Yanxiang
• Chi Min-Hwa

Classifications

• H03C3/245

  by using semiconductor elements · CPC title

• H03C3/145 Primary

  by using semiconductor elements · CPC title

• H03C3/02 Primary

  Details · CPC title

• H03D7/125

  with field effect transistors · CPC title

• H01L29/66977

  Electricity · mapped topic