Semiconductor devices including a gate core and a fin active core and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9673300-B2
Application number	US-201514820860-A
Country	US
Kind code	B2
Filing date	Aug 7, 2015
Priority date	Oct 17, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Semiconductor devices and methods of fabricating the same are provided. The methods may include forming an isolation region defining a fin active region, forming a sacrificial field gate pattern on the isolation region and forming a sacrificial fin gate pattern on the fin active region. The method may also include forming a field gate cut zone comprising a first recess exposing a surface of the isolation region and a fin active cut zone comprising a second recess exposing a surface of the fin active region, forming a fin active recess in the second recess of the fin active cut zone and forming a field gate core and a fin active core by forming an insulation material in the first recess of the field gate cut zone and the fin active recess, respectively.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, comprising:
forming an isolation region defining a fin active region on a substrate;
forming a sacrificial field gate pattern on the isolation region and forming a sacrificial fin gate pattern on the fin active region;
forming a first interlayer insulating layer between the sacrificial field gate pattern and the sacrificial fin gate pattern;
forming a field gate cut zone comprising a first recess exposing a surface of the isolation region by removing a first portion of the sacrificial field gate pattern and a fin active cut zone comprising a second recess exposing a surface of the fin active region by removing a first portion of the sacrificial fin gate pattern;
forming a fin active recess by removing the fin active region exposed in the second recess of the fin active cut zone;
forming a field gate core and a fin active core by forming an insulation material in the first recess of the field gate cut zone and the fin active recess, respectively;
forming a field gate electrode opening by removing a second portion of the sacrificial field gate pattern and forming a fin gate electrode opening by removing a second portion of the sacrificial fin gate pattern; and
forming a field gate pattern in the field gate electrode opening and forming a fin gate pattern in the fin gate electrode opening.

2. The method of claim 1 , further comprising forming a base insulating layer between the fin active region and the sacrificial fin gate pattern using a deposition process.

3. The method of claim 1 , wherein the forming of the isolation region comprises:
forming a trench comprising a deep trench and a shallow trench in the substrate; and
forming a trench insulation material filling the deep trench and partially filling the shallow trench.

4. The method of claim 1 , wherein the sacrificial field gate pattern and the sacrificial fin gate pattern comprise polysilicon, the first interlayer insulating layer comprises silicon oxide, and the field gate core and the fin active core comprise silicon nitride.

5. The method of claim 1 , further comprising:
forming a fin gate cut zone comprising a third recess by removing a third portion of the sacrificial fin gate pattern; and
forming a fin gate core by forming the insulation material in the third recess of the fin gate cut zone.

6. The method of claim 1 , further comprising:
forming a sacrificial dummy gate pattern on the isolation region;
forming a dummy gate electrode opening by removing the sacrificial dummy gate pattern; and
forming a dummy gate pattern in the dummy gate electrode opening.

7. The method of claim 1 , further comprising:
forming a sacrificial butting gate pattern overlapping both the isolation region and the fin active region;
forming a butting gate electrode opening by removing the sacrificial butting gate pattern; and
forming a butting gate pattern in the butting gate electrode opening.

8. The method of claim 1 , further comprising:
forming a source/drain region in the fin active region adjacent the fin gate pattern;
forming a contact pattern extending through the first interlayer insulating layer and connecting to the source/drain region;
forming a second interlayer insulating layer on the contact pattern; and
forming a via pattern extending through the second interlayer insulating layer and connecting to the contact pattern.

9. The method of claim 8 , wherein the forming of the source/drain region comprises performing an epitaxial growth process, and wherein the contact pattern comprises a silicide layer directly on the source/drain region, a contact barrier layer on the silicide layer, and a contact plug on the contact barrier layer.

10. A method of fabricating a semiconductor device, comprising:
forming an isolation region in a substrate, the substrate comprising a field area and an active area, and the isolation region defining a fin active region in the active area;
forming a sacrificial first field gate pattern on the isolation region of the field area and forming a sacrificial first fin gate pattern and a sacrificial second fin gate pattern on the fin active region and the isolation region of the active area;
forming a first field gate cut zone comprising a first recess exposing the isolation region by removing a portion of the sacrificial first field gate pattern and a fin gate cut zone comprising a second recess exposing the fin active region by removing a portion of the sacrificial second fin gate pattern;
forming a fin active recess by removing a portion of the fin active region exposed in the second recess of the fin gate cut zone;
forming a first field gate core, a fin gate core, and a fin active core in the first recess of the first field gate cut zone, the second recess of the fin gate cut zone, and the fin active recess, respectively, wherein the first field gate core, the fin gate core, and the fin active core comprise the same material;
forming a first fin gate electrode opening by removing a portion of the sacrificial first fin gate pattern; and
forming a first fin gate pattern in the first fin gate electrode opening.

11. The method of claim 10 , further comprising:
forming a sacrificial second field gate pattern on the isolation region of the field area;
forming a second field gate cut zone comprising a third recess by removing a portion of the sacrificial second field gate pattern; and
forming a second field gate core in the third recess of the second field gate cut zone.

12. The method of claim 11 , wherein the first field gate core, the fin gate core, and the fin active core comprise silicon nitride, and the second field gate core comprises silicon oxide.

13. The method of claim 10 , further comprising:
forming a sacrificial dummy field gate pattern on the isolation region of the field area;
forming a dummy field gate electrode opening by removing the sacrificial dummy field gate pattern; and
forming a dummy field gate pattern in the dummy field gate electrode opening.

14. The method of claim 10 , further comprising:
forming a sacrificial butting gate pattern on the isolation region and the fin active region of the active area;
forming a butting gate electrode opening by removing the sacrificial butting gate pattern; and
forming a butting gate pattern in the butting gate electrode opening.

15. The method of claim 10 , wherein upper surfaces of the first field gate core, the fin gate core, the fin active core, and the first fin gate pattern are coplanar.

16. A method of fabricating a semiconductor device, comprising:
forming a fin active region in a first region of a substrate, the substrate comprising the first region and a second region;
forming an isolation region in the first region and the second region of the substrate, the isolation region being adjacent the fin active region;
forming a first gate line in the first region of the substrate, the first gate line traversing the fin active region and extending on the isolation region;
forming a second gate line extending on the isolation region in the second region of the substrate;
concurrently removing a portion of the first gate line disposed on the fin active region to form a first recess in the first gate line and a portion of the second gate line to form a second recess in the second gate line;
removing a portion of the fin active region exposed by the first recess of the first gate line to form a third recess in the fin active region; and
forming a first insulating core pattern in the first and third recesses and a second insulating cor

Assignees

• Ha Seungseok
• Bai Keunhee
• Yeo Kyounghwan
• Park Eunsil
• Shin Heonjong
• Samsung Electronics Co Ltd

Inventors

• Ha Seungseok
• Bai Keunhee
• Yeo Kyounghwan
• Park Eunsil
• Shin Heonjong

Classifications

• H10W10/0143 Primary

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D30/6215

  having multiple independently-addressable gate electrodes · CPC title

• H10D30/792

  comprising applied insulating layers, e.g. stress liners · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title