Dual oxide trench gate power MOSFET using oxide filled trench

Patent metadata

Field	Value
Publication number	US-9673289-B2
Application number	US-201514880886-A
Country	US
Kind code	B2
Filing date	Oct 12, 2015
Priority date	Dec 22, 2013
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A power MOSFET device including a semiconductor layer, an active trench formed in the semiconductor layer and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the active trench by a liner oxide layer having a first thickness, and a termination trench formed in the semiconductor layer apart from the active trench and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the termination trench by the liner oxide layer having a second thickness. In one embodiment, the second thickness is greater than the first thickness. In another embodiment, the trench gate in each of the active trench and the termination trench is formed as a single polysilicon layer.

First claim

What is claimed is:

1. A power metal-oxide-silicon field effect transistor (MOSFET) device, comprising:
a semiconductor layer of a first conductivity type;
an active trench formed in the semiconductor layer, the active trench having a first trench depth and housing a dual oxide thickness trench gate structure including a first trench gate formed in the active trench, the first trench gate being isolated from a sidewall of the semiconductor layer by a gate oxide layer in an upper portion of the active trench and being isolated from the sidewall of the semiconductor layer by a first liner oxide layer in a bottom portion of the active trench, the first liner oxide layer being formed between the first trench gate and the sidewall of the semiconductor layer in a lateral direction, the first liner oxide layer being thicker than the gate oxide layer, a bottom of the first trench gate being isolated from a bottom of the active trench by the first liner oxide layer having a first thickness; and
a termination trench formed in the semiconductor layer apart from the active trench, the termination trench having a second trench depth deeper than the first trench depth and housing a dual oxide thickness trench gate structure including a second trench gate formed in the termination trench, the second trench gate being isolated from the sidewall of the semiconductor layer on a first side of the termination trench by a first sidewall oxide layer in an upper portion of the termination trench and by a second liner oxide layer in a bottom portion of the termination trench, the second liner oxide layer being formed between the second trench gate and the sidewall of the semiconductor layer on the first side in a lateral direction, the second liner oxide layer being thicker than the first sidewall oxide layer, the second trench gate being isolated from the sidewall of the semiconductor layer on a second, opposite side of the termination trench by a second sidewall oxide layer, a bottom of the second trench gate being isolated from a bottom of the termination trench by the second liner oxide layer having a second thickness greater than the first thickness.

2. The power MOSFET device of claim 1 , wherein the first sidewall oxide layer in the termination trench is formed as a gate oxide layer same as the gate oxide layer formed in the active trench.

3. The power MOSFET device of claim 2 wherein the gate oxide layer and the first sidewall oxide layer are both formed by thermal oxidation of the semiconductor layer along the upper portion of the respective active trench and termination trench.

4. The power MOSFET device of claim 1 , wherein the first liner oxide layer, the second liner oxide layer and the second sidewall oxide layer each comprises a high density plasma oxide layer.

5. The power MOSFET device of claim 1 , further comprising:
a body region of a second conductivity type formed in the semiconductor layer adjacent to the upper portion of the active trench and the first side of the termination trench;
a source region of the first conductivity type formed in the body region and adjacent to the upper portion of the active trench and the first side of the termination trench; and
a contact to the body region and the source region.

6. The power MOSFET device of claim 1 , wherein the semiconductor layer comprises a lightly doped semiconductor substrate of the first conductivity type, the semiconductor substrate forming a drift region of the power MOSFET device, the power MOSFET device further comprising:
a heavily doped drain contact region formed on a bottom portion of the semiconductor substrate.

7. The power MOSFET device of claim 1 , wherein the second sidewall oxide layer of the termination trench has a thickness greater than a thickness of the second liner oxide layer formed on the first side of the termination trench.

8. The power MOSFET device of claim 1 , wherein the second sidewall oxide layer of the termination trench has a thickness sufficient to provide edge termination for the power MOSFET device.

9. The power MOSFET device of claim 1 , wherein the first conductivity type is N-type and a second conductivity type is P-type.

10. The power MOSFET device of claim 1 , wherein the active trench houses a multiple oxide thickness trench gate structure including the first trench gate formed in the active trench, the first trench gate being isolated from the semiconductor layer by the gate oxide layer in the upper portion of the active trench and being isolated from the semiconductor layer by the first liner oxide layer in the bottom portion of the active trench, the first liner oxide layer forming a staggered oxide structure having increasing oxide thickness from the gate oxide layer to the bottom of the active trench.

11. The power MOSFET device of claim 1 , wherein the termination trench houses a multiple oxide thickness trench gate structure including the second trench gate formed in the termination trench, the second trench gate being isolated from the semiconductor layer on the first side of the termination trench by the first sidewall oxide layer in the upper portion of the termination trench and by the second liner oxide layer in the bottom portion of the termination trench, the second liner oxide layer being thicker than the first sidewall oxide layer, the second trench gate being isolated from the semiconductor layer on the second, opposite side of the termination trench by the second sidewall oxide layer, the second liner oxide layer forming a staggered oxide structure on the first side of the termination trench having increasing oxide thickness from the first sidewall oxide layer to the bottom of the termination trench and the second sidewall oxide layer forming a staggered oxide structure having increasing oxide thickness on the second side of the termination trench.

12. The power MOSFET device of claim 1 , wherein the active trench comprises a single polysilicon layer as the first trench gate inside the active trench.

13. The power MOSFET device of claim 1 , wherein the termination trench comprises a single polysilicon layer as the second trench gate inside the termination trench.

14. A power metal-oxide-silicon field effect transistor (MOSFET) device, comprising:
a semiconductor layer of a first conductivity type;
an active trench formed in the semiconductor layer, the active trench having a first trench depth and housing a dual oxide thickness trench gate structure including a first trench gate formed in the active trench, the first trench gate being isolated from a sidewall of the semiconductor layer by a gate oxide layer in an upper portion of the active trench and being isolated from the sidewall of the semiconductor layer by a first liner oxide layer in a bottom portion of the active trench, the first liner oxide layer being formed between the first trench gate and the sidewall of the semiconductor layer in a lateral direction, the first liner oxide layer being thicker than the gate oxide layer, a bottom of the first trench gate being isolated from to a bottom of the active trench by the first liner oxide layer having a first thickness, the active trench housing only one polysilicon layer; and
a termination trench formed in the semiconductor layer apart from the active trench, the termination trench having a second trench depth deeper than the first trench depth and housing a dual oxide thickness trench gate structure including a second trench gate formed in the termination trench, the second trench gate being isolated from the sidewall of the semiconductor layer on a first side of the termination trench by a first sidewall oxide layer in an uppe

Assignees

• Alpha & Omega Semiconductor

Inventors

• Calafut Daniel
• Bobde Madhur
• Lee Yeeheng
• Chang Hong

Classifications

• H01L29/42368 Primary

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L29/4916

  Electricity · mapped topic

• H01L29/8725

  Electricity · mapped topic