Methods of forming vertical field-effect transistor with self-aligned contacts for memory devices with planar periphery/array and intermediate structures formed thereby

Patent metadata

Field	Value
Publication number	US-9673102-B2
Application number	US-201113078274-A
Country	US
Kind code	B2
Filing date	Apr 1, 2011
Priority date	Apr 1, 2011
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.

First claim

What is claimed as new and desired to be protected by Letters Patent of the United States is:

1. A method of forming a structure of a memory device having an array portion including a plurality of vertical array transistors and a periphery region including peripheral circuit transistors, the method comprising:
forming at least one trench in the periphery region of a substrate and at least one trench in the array portion of the substrate concurrently, the at least one trench in the periphery region producing one or more fins in the periphery region and the at least one trench in the array portion producing one or more fins in the array portion;
forming each of the peripheral circuit transistors over a fin of the one or more fins in the periphery region;
forming the plurality of vertical array transistors from the one or more fins in the array portion, each of the plurality of vertical array transistors having a self-aligned contact; and
forming a phase change memory cell over the self-aligned contact of each of the vertical array transistors.

2. The method of claim 1 , wherein an upper surface of the peripheral circuit transistors and an upper surface of the phase change memory cells are within 500 Å of average elevation.

3. The method of claim 1 , wherein an upper surface of the peripheral circuit transistors and an upper surface of the phase change memory cells are within 200 Å of average elevation.

4. The method of claim 1 , wherein an upper surface of the peripheral circuit transistors and an upper surface of the phase change memory cells are coplanar.

5. The method of claim , wherein forming the phase change memory cells comprises:
forming a plurality of silicide contacts by silicidation of the self-aligned contact of each of the vertical array transistors; and
depositing a phase-change material over each of the plurality of silicide contacts.

6. The method of claim 1 , wherein forming the phase change memory cells comprises:
depositing metal on the self-aligned contact of each of the vertical array transistors;
forming a recess in an upper surface of the deposited metal on each of the vertical array transistors; and
depositing a phase-change material over the deposited metal on each of the vertical array transistors.

7. A method of forming a structure of a memory device having an array portion including a plurality of vertical array transistors and a periphery region including peripheral circuit transistor structures, the method comprising:
forming the peripheral circuit transistor structures in the periphery region;
forming the plurality of vertical array transistors in the array portion, each of the plurality of vertical array transistors having a self-aligned contact; and
forming a phase change memory cell over the self-aligned contact of each of the vertical array transistors,
wherein forming the plurality of vertical array transistors comprises:
doping an upper surface of a substrate in the array portion;
forming an oxide over the array portion and the periphery region, wherein the oxide extends above an upper surface of the peripheral circuit transistor structures;
forming a first plurality of trenches in the array portion, the first plurality of trenches extending through the oxide to the doped upper surface of the substrate;
growing epitaxial silicon within the first plurality of trenches;
forming a patterned resist material mask on the array portion, in a direction perpendicular to a direction of formation of the first plurality of trenches, and forming the resist material mask over the entire periphery region;
etching unmasked areas of the oxide and unmasked areas of the epitaxial silicon within the first plurality of trenches to form a second plurality of trenches, the second plurality of trenches extending through the oxide and epitaxial silicon to the doped upper surface of the substrate, resulting in a plurality of silicon pillars in the array portion;
removing the resist material;
forming a gate oxide on exposed surfaces of the silicon pillars and on exposed portions of the doped upper surface of the substrate; and
forming side gates on the gate oxide.

8. The method of claim 7 , wherein doping the upper surface of the substrate comprises an n-type doping.

9. The method of claim 7 , wherein the oxide comprises silicon dioxide.

10. The method of claim 7 , wherein forming the side gates comprises:
depositing a gate material on sides of the gate oxide covered silicon pillars; and
etching the gate material to be recessed below a top surface of the gate oxide covered silicon pillars.

11. The method of claim 10 , wherein the gate material is TiN.

12. The method of claim 10 , wherein depositing the gate material comprises atomic layer deposition and etching the gate material comprises a spacer etch process.

13. The method of claim 7 , wherein forming the phase change memory cells comprises:
forming a plurality of silicide contacts by silicidation of the self-aligned contact of each of the vertical array transistors; and
depositing a phase-change material over each of the plurality of silicide contacts.

14. The method of claim 13 , wherein the phase-change material comprises germanium, antimony, and tellurium.

15. The method of claim 7 , wherein forming the phase change memory cells comprises:
depositing metal on the self-aligned contact of each of the vertical array transistors;
forming a recess in an upper surface of the deposited metal on each of the vertical array transistors; and
depositing a phase-change material over the deposited metal on each of the vertical array transistors.

16. A method of forming a structure of a memory device having an array portion including a plurality of vertical array transistors and a periphery region including peripheral circuit transistor structures, the method comprising:
forming the peripheral circuit transistor structures in the periphery region;
forming the plurality of vertical array transistors in the array portion, each of the plurality of vertical array transistors having a self-aligned contact; and
forming a phase change memory cell over the self-aligned contact of each of the vertical array transistors,
wherein forming the plurality of vertical array transistors comprises:
doping an upper surface of a substrate in the array portion;
forming an oxide over the array portion and the periphery region, wherein the oxide extends above an upper surface of the peripheral circuit transistor structures;
forming a plurality of trenches through the oxide to the doped upper surface of the substrate;
growing epitaxial silicon within the plurality of trenches to form a plurality of silicon pillars;
etching the oxide to expose sides of the plurality of silicon pillars;
forming a gate oxide on exposed surfaces of the silicon pillars and on exposed portions of the doped upper surface of the substrate; and
forming all around gates on the silicon pillars.

17. The method of claim 16 , wherein forming the all around gates comprises:
depositing a gate material on the gate oxide; and
etching the gate material to be recessed below a top surface of the gate oxide.

18. The method of claim 17 , wherein the gate material is TiN.

19. A method of forming a structure of a memory device having an array portion including a plurality of vertical array transistors and a periphery region including peripheral circuit transistor structures, the method comprising:
forming the peripheral circuit transistor structures in the periphery region;
forming the

Assignees

• Liu Jun
• Tang Sanh D
• Wells David H
• Micron Technology Inc

Inventors

• Liu Jun
• Tang Sanh D
• Wells David H

Classifications

• H01L27/2454

  Electricity · mapped topic

• H01L27/105

  Electricity · mapped topic

• H01L45/144

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L45/1233

  Electricity · mapped topic