System and method for integrated circuits with cylindrical gate structures

Patent metadata

Field	Value
Publication number	US-9673060-B2
Application number	US-201615157366-A
Country	US
Kind code	B2
Filing date	May 17, 2016
Priority date	Sep 28, 2009
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A device and method for integrated circuits with surrounding gate structures are disclosed. The device includes a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure is doped with a first conductivity type and includes a source region at one distal end and a drain region at the opposite distal end. The device further includes a gate structure overlying a channel region disposed between the source and drain regions of the fin structure. The fin structure has a rectangular cross-sectional bottom portion and an arched cross-sectional top portion. The arched cross-sectional top portion is semi-circular shaped and has a radius that is equal to or smaller than the height of the rectangular cross-sectional bottom portion. The source, drain, and the channel regions each are doped with dopants of the same polarity and the same concentration.

First claim

What is claimed is:

1. A method for fabricating a transistor device, the method comprising:
providing a semiconductor substrate;
forming an elongated semiconductor structure overlying a region of the semiconductor substrate along a first direction, the elongated semiconductor structure having a rectangular cross-section;
etching the elongated semiconductor structure to form an arched cross-section top portion and a rectangular cross-section bottom portion;
implanting dopants of a first-type impurity in the elongated semiconductor structure;
forming a dielectric layer on the elongated semiconductor structure;
depositing a conductive material on the dielectric layer; and
masking and etching the conductive material and the dielectric layer to form a gate electrode for the transistor device.

2. The method of claim 1 , wherein the semiconductor substrate comprises:
a silicon substrate;
a silicon oxide layer overlying the silicon substrate; and
a silicon layer overlying the silicon oxide layer.

3. The method of claim 1 , further comprising:
implanting dopants of a second-type impurity in the region of the semiconductor substrate the elongated semiconductor structure prior to forming the elongated semiconductor structure.

4. The method of claim 1 further comprising:
etching around the elongated semiconductor structure to form a trench at a periphery of a low end of the rectangular cross-section;
filling the trench with an insulating material to form an insulating structure, wherein the insulating structure is formed prior to implanting dopants of the first-type impurity in the elongated semiconductor structure.

5. The method of claim 4 , wherein the arched cross-section top portion comprises a semi-circular shape having a radius and the rectangular cross-section bottom portion comprises a height, the height being equal to or greater than the radius.

6. The method of claim 1 wherein the elongated semiconductor structure comprises silicon, germanium, silicon germanium, or other III or V group semiconductor materials.

7. The method of claim 1 , wherein etching the elongated semiconductor structure comprises:
oxidizing the elongated semiconductor structure; and
removing oxidized portions of the elongated semiconductor structure.

8. The method of claim 7 further comprising annealing the elongated semiconductor structure.

9. The method of claim 1 , wherein etching the elongated semiconductor structure comprises:
thermally oxidizing the elongated semiconductor structure comprising a silicon material, and
removing the oxidized material using a diluted hydrofluoric acid.

10. The method of claim 9 further comprising:
hydrogen annealing at a temperature range from about 1000° C. to about 1200° C. and for a time period of about 5 minutes to 30 minutes.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Xiao De Yuan
• Chen Guo Qing
• Lee Roger
• Yen Chin Fu
• Xing Su
• Huang xiao lu
• Yang yong sheng

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title