Radiation upset detection

Patent metadata

Field	Value
Publication number	US-9672880-B2
Application number	US-201414511709-A
Country	US
Kind code	B2
Filing date	Oct 10, 2014
Priority date	Jun 16, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A radiation upset detector is provided. The radiation upset detector includes at least one radiation sensitive memory initialized with at least one respective known-signature word; and at least one radiation hardened logic circuitry communicatively coupled to the at radiation sensitive memory to check the known-signature word at at least a kHz rate to detects errors. Responsive to detecting an error in the known-signature word in the radiation sensitive memory, the radiation hardened logic circuitry sends an action command. At least one of: a memory size of the memory; a number of circuits in the logic circuitry; a clock rate for the checking the known-signature word; and at least one corruption threshold is selected based on system reliability requirements of the protected system including at least one of: an overall operational reliability requirement of the protected system; a probability of detection success; false alarm rates; and a required speed of detection.

First claim

What is claimed is:

1. A radiation upset detector for use with a protected system, the radiation upset detector comprising:
at least one radiation sensitive memory initialized with at least one respective known-signature word; and
at least one radiation hardened logic circuitry communicatively coupled to exchange data with the at least one respective radiation sensitive memory in order to check the at least one known-signature word at at least a kHz rate to detect errors,
wherein at least a portion of the at least one radiation hardened logic circuitry is radiation hardened to withstand radiation events,
wherein responsive to detecting an error in the known-signature word in the respective at least one radiation sensitive memory, the at least one radiation hardened logic circuitry is further configured to send an action command, and
wherein a memory size of the at least one radiation sensitive memory; a number of circuits in the at least one radiation hardened logic circuitry; a clock rate for the checking the at least one known-signature word; and at least one corruption threshold are selected based on system reliability requirements of the protected system including at least one of:
an overall operational reliability requirement of the protected system; a probability of detection success; false alarm rates; and a required speed of detection.

2. The radiation upset detector of claim 1 , wherein the action command sent from the at least one radiation hardened logic circuitry is a command to re-initialize the respective at least one radiation sensitive memory.

3. The radiation upset detector of claim 1 , wherein the action command sent from the at least one radiation hardened logic circuitry is a command to initiate a reset in at least one component in the protected system communicatively coupled to the at least one radiation hardened logic circuitry.

4. The radiation upset detector of claim 1 , wherein the at least one radiation sensitive memory is a single radiation sensitive memory, wherein the at least one radiation hardened logic circuitry includes a plurality of radiation hardened logic circuitry.

5. The radiation upset detector of claim 4 , further comprising:
master radiation hardened logic circuitry, wherein at least one of the plurality of radiation hardened logic circuitry sends at least one signal responsive to detecting the error in the known-signature word to the master radiation hardened logic circuitry, and wherein the master radiation hardened logic circuitry outputs the action command responsive to the at least one signal from the at least one of the plurality of radiation hardened logic circuitry.

6. The radiation upset detector of claim 4 , wherein a subset of the plurality of radiation hardened logic circuitry is communicatively coupled to send at least one signal to one of the other radiation hardened logic circuitry in the plurality of radiation hardened logic circuitry, and wherein the one of the other radiation hardened logic circuitry outputs the action command responsive to the at least one signal from the subset of the plurality of radiation hardened logic circuitry.

7. The radiation upset detector of claim 4 , wherein a first radiation hardened logic circuitry of the plurality of radiation hardened logic circuitry checks a first-known-signature word at at least a kHz rate in a first portion of the single radiation sensitive memory, and wherein a second radiation hardened logic circuitry of the plurality of radiation hardened logic circuitry checks a second-known-signature word at at least a kHz rate in a second portion of the single radiation sensitive memory.

8. The radiation upset detector of claim 1 , wherein the at least one radiation hardened logic circuitry detects a first type of error based on exceeding a first corruption threshold, wherein the action command sent from the at least one radiation hardened logic circuitry responsive to detecting the first type of error includes a command to initiate a reset in at least one component in the protected system communicatively coupled to the at least one radiation hardened logic circuitry and includes a command to re-initialize the respective at least one radiation sensitive memory.

9. The radiation upset detector of claim 1 , wherein the at least one radiation hardened logic circuitry detects a second type of error based on data corruption being less than a first corruption threshold and exceeding a second corruption threshold.

10. The radiation upset detector of claim 9 , wherein the action command sent from the at least one radiation hardened logic circuitry responsive to detecting the second type of error is a command to re-initialize the respective at least one radiation sensitive memory.

11. A method to protect a protected system from a radiation event, the method comprising:
initializing at least one radiation sensitive memory with at least one known-signature word;
checking the at least one known-signature word in the at least one radiation sensitive memory for errors in at least one radiation hardened logic circuitry at at least a kHz rate;
detecting an error in the at least one known-signature word in the respective at least one radiation hardened logic circuitry; and
sending an action command responsive to detecting the error,
wherein a memory size of the at least one radiation sensitive memory; a number of circuits in the at least one radiation hardened logic circuitry; a clock rate for the checking the at least one known-signature word; and at least one corruption threshold are selected based on system reliability requirements of the protected system including at least one of:
an overall operational reliability requirement of the protected system; a probability of detection success; false alarm rates; and a required speed of detection.

12. The method of claim 11 , wherein sending the action command responsive to detecting the error comprises:
sending a re-initialization signal to re-initialize the respective at least one radiation sensitive memory from the at least one radiation hardened logic circuitry to re-initialize at least a portion of the protected system based on a detection of the error.

13. The method of claim 12 , wherein sending the action command responsive to detecting the error comprises:
sending a reset signal to initiate a reset in at least one component in the protected system communicatively coupled to the at least one radiation hardened logic circuitry.

14. The method of claim 11 , wherein sending the action command responsive to detecting the error comprises:
sending a reset signal to initiate a reset in at least one component in the protected system communicatively coupled to the at least one radiation hardened logic circuitry.

15. The method of claim 11 , wherein initializing the at least one radiation sensitive memory with the at least one known-signature word comprises:
initializing a first radiation sensitive memory with a first-known-signature word; and
initializing a second radiation sensitive memory with a second-known-signature word, wherein checking the at least one known-signature word in the radiation sensitive memory for errors in the at least one radiation hardened logic circuitry comprises:
checking the first-known-signature word in the first radiation sensitive memory for errors in first logic circuitry at at least a kHz rate; and
checking the second-known-signature word in the second radiation sensitive memory for errors in second logic circuitry at at least a kHz rate.

16. The method of claim 11 , wherein initializing the at least one radiation sensit

Assignees

• Honeywell Int Inc

Inventors

• Buck Timothy Merrill
• Wiley Paris D

Classifications

• G11C5/005

  Circuit means for protection against loss of information of semiconductor storage devices · CPC title

• G11C11/4125

  Cells incorporating circuit means for protecting against loss of information · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C7/20 Primary

  Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory · CPC title