Pixel circuit and display panel
US-2024428730-A1 · Dec 26, 2024 · US
US9672769B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9672769-B2 |
| Application number | US-201414523796-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 24, 2014 |
| Priority date | Feb 27, 2014 |
| Publication date | Jun 6, 2017 |
| Grant date | Jun 6, 2017 |
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A display apparatus includes a display panel having a first portion and a second portion, a gate driver configured to drive a first gate line group in the first portion of the display panel starting at a first scan start point and to drive a second gate line group in the second portion of the display panel starting at a second scan start point, the second scan start point being different from the first scan start point, a first data driver configured to output a first data voltage to a first data line group in the first portion and a second data driver configured to output a second data voltage to a second data line group in the second portion.
Opening claim text (preview).
What is claimed is: 1. A display apparatus comprising: a display panel having a first portion comprising a first plurality of pixels and a second portion comprising a second plurality of pixels; a gate driver configured to drive a first gate line group in the first portion of the display panel sequentially from a first gate line of the first gate line group to a last gate line of the first gate line group starting at a first scan start point and to drive a second gate line group in the second portion of the display panel sequentially from a first gate line of the second gate line group to a last gate line of the second gate line group starting at a second scan start point, the second scan start point being different from the first scan start point, the first plurality of pixels comprising each of the pixels coupled to the first gate line group and the second plurality of pixels comprising each of the pixels coupled to the second gate line group; a first data driver configured to output a first data voltage to a first data line group in the first portion, the first data line group being coupled to each pixel of the first plurality of pixels; and a second data driver configured to output a second data voltage to a second data line group in the second portion, the second data line group being coupled to each pixel of the second plurality of pixels, wherein the first portion is an upper portion of the display panel and the second portion is a lower portion of the display panel, wherein the last gate line of the first gate line group is adjacent to the first gate line of the second gate line group, and wherein the second scan start point is earlier than the first scan start point. 2. The display apparatus of claim 1 , wherein the second scan start point is earlier than the first scan start point by a vertical blank duration of an input image data. 3. The display apparatus of claim 2 , wherein the first portion and the second portion are continuously scanned. 4. The display apparatus of claim 2 , wherein the first data driver is configured to output one of a plurality of data voltages applied during an active duration of the input image data to the first portion during the vertical blank duration. 5. The display apparatus of claim 2 , wherein the first data driver is configured to output a repair pixel voltage to repair a pixel of the first portion during the vertical blank duration. 6. The display apparatus of claim 2 , wherein a first vertical blank duration corresponding to the first portion is substantially the same as a second vertical blank duration corresponding to the second portion. 7. The display apparatus of claim 2 , wherein the vertical blank duration varies on a frame-by-frame basis according to the input image data. 8. The display apparatus of claim 1 , wherein the gate driver comprises: a first gate driver connected to the first gate line group; and a second gate driver connected to the second gate line group. 9. The display apparatus of claim 8 , further comprising a timing controller configured to control driving timings of the gate driver, the first data driver, and the second data driver, wherein the timing controller is configured to output a first vertical start signal to the first gate driver and a second vertical start signal to the second gate driver, and wherein the timing controller is configured to output the second vertical start signal before outputting the first vertical start signal. 10. The display apparatus of claim 1 , wherein the gate driver is commonly connected to the first gate line group and the second gate line group, and wherein a first fan-out resistance between the gate driver and a gate line of the first gate line group is different from a second fan-out resistance between the gate driver and a gate line of the second gate line group. 11. The display apparatus of claim 10 , wherein the gate driver is closer to the second portion than to the first portion. 12. The display apparatus of claim 1 , further comprising a timing controller configured to control driving timings of the gate driver, the first data driver, and the second data driver, wherein the timing controller comprises: an image dividing part configured to divide an input image data into a first image data corresponding to the first portion and a second image data corresponding to the second portion; and an image rearranging part configured to rearrange the first image data in a data type of the first data driver and the second image data in a data type of the second data driver. 13. A method of driving a display apparatus comprising a plurality of pixels, the method comprising: scanning a first gate line group in a first portion of a display panel sequentially from a first gate line of the first gate line group to a last gate line of the first gate line group starting at a first scan start point, the first portion of the display panel comprising a first plurality of pixels, the first plurality of pixels comprising each of the pixels coupled to the first gate line group; scanning a second gate line group in a second portion of the display panel sequentially from a first gate line of the second gate line group to a last gate line of the second gate line group starting at a second scan start point different from the first scan start point, the second portion of the display panel comprising a second plurality of pixels, the second plurality of pixels comprising each of the pixels coupled to the second gate line group; outputting a first data voltage to a first data line group in the first portion of the display panel, the first data line group being coupled to each pixel of the first plurality of pixels; and outputting a second data voltage to a second data line group in the second portion of the display panel, the second data line group being coupled to each pixel of the second plurality of pixels, wherein the first portion is an upper portion of the display panel and the second portion is a lower portion of the display panel, wherein the last gate line of the first gate line group is adjacent to the first gate line of the second gate line group, and wherein the second scan start point is earlier than the first scan start point. 14. The method of claim 13 , wherein the second scan start point is earlier than the first scan start point by a vertical blank duration of an input image data. 15. The method of claim 14 , wherein the first portion and the second portion are continuously scanned. 16. The method of claim 14 , wherein a first vertical blank duration corresponding to the first portion is substantially the same as a second vertical blank duration corresponding to the second portion. 17. The method of claim 14 , wherein the vertical blank duration varies on a frame-by-frame basis according to the input image data.
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