High speed processing of financial information using FPGA devices

Patent metadata

Field	Value
Publication number	US-9672565-B2
Application number	US-201314092019-A
Country	US
Kind code	B2
Filing date	Nov 27, 2013
Priority date	Jun 19, 2006
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Methods and systems for processing financial market data using a reconfigurable logic device are disclosed. Various operations such as volume weighted average price (VWAP) operations can be performed on the financial market data using firmware logic deployed on the reconfigurable logic device to accelerate the speed of processing.

First claim

What is claimed is:

1. An apparatus for processing financial market data, the apparatus comprising:
a computer system comprising a processor and a reconfigurable logic device that are configured to cooperate with each other to process streaming financial market data relating to a plurality of financial instruments;
wherein the processor is configured to (1) execute an operating system that includes a user space for a user mode and a kernel space for a kernel mode, (2) receive a feed of streaming financial market data through a network protocol stack, wherein the streaming financial market data comprises volume and price information corresponding to a plurality of financial instruments, (3) use shared memory that is mapped into the kernel space and the user space to store financial market data within the streaming financial market data while the financial market data is being processed by the processor, and (4) facilitate DMA transfers of the stored financial market data to the reconfigurable logic device from the shared memory; and
the reconfigurable logic device having firmware logic deployed thereon that is configured to (1) receive financial market data from the shared memory via the DMA transfers, and (2) compute a volume weighted average price (VWAP) for each of a plurality of the financial instruments corresponding to the received financial market data based on volume and pricing information within the received financial market data.

2. The apparatus of claim 1 wherein the firmware logic is further configured to store the computed VWAPs in a memory in association with the financial instruments to which the computed VWAPs pertain.

3. The apparatus of claim 2 wherein the streaming financial market data comprises a plurality of fields, the fields comprising a price field and a trade size field, and wherein the firmware logic is further configured to compute the VWAPs for the financial instruments based on the price and trade size fields within the received financial market data pertaining to those financial instruments.

4. The apparatus of claim 3 wherein the firmware logic comprises a calculation engine, the calculation engine deployed on the reconfigurable logic device as a firmware application module within a pipeline of a plurality of firmware application modules.

5. The apparatus of claim 4 wherein a firmware application module in the pipeline upstream from the calculation engine comprises a filter, the filter configured to filter financial market data within the received financial market data based on a plurality of criteria to determine which financial market data is to be processed by the downstream calculation engine.

6. The apparatus of claim 5 wherein the plurality of criteria comprise at least one member of the group consisting of trade size, trade type, and market conditions.

7. The apparatus of claim 4 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

8. The apparatus of claim 4 wherein the firmware application modules further comprise an alert generation engine within the pipeline downstream from the calculation engine, the alert generation engine configured to generate an alert for consumption by a downstream application in response to a specified condition being met.

9. The apparatus of claim 2 further comprising the memory in which the computed VWAPs are stored in association with financial instruments, the memory for storing a plurality of records associated with a plurality of financial instruments, the records comprising a plurality of fields, at least a plurality of the financial instrument records including a field for storing the computed VWAP for its associated financial instrument.

10. The apparatus of claim 9 wherein the memory comprises memory external to the reconfigurable logic device.

11. The apparatus of claim 9 wherein the streaming financial market data comprises a symbol field that includes a symbol string for identifying the financial instruments associated with the volume and pricing information, and wherein the firmware logic comprises a plurality of firmware application modules (FAMs) arranged in a pipeline, the pipeline comprising a first FAM and a second FAM, the second FAM being downstream from the first FAM;
wherein the first FAM is configured to (1) map the symbol strings within the received financial market data to a plurality of internal symbol IDs for the records corresponding to the financial instruments corresponding to those symbol strings, and (2) generate a plurality of output messages comprising the internal symbol IDs; and
wherein the second FAM is configured to (1) receive the internal symbol IDs and the financial market data corresponding to the received internal symbol IDs, and (2) perform a plurality of calculation operations in response to the received internal symbol IDs and the received corresponding financial market data to compute a plurality of VWAPs for the financial instrument records corresponding to the received internal symbol IDs; and
wherein the first FAM and the second FAM are configured to operate simultaneously with respect to each other in a pipelined fashion.

12. The apparatus of claim 11 wherein the second FAM is further configured to compute the VWAPs for the financial instrument records at hardware processing speeds as financial market data and internal symbol IDs are received by the second FAM.

13. The apparatus of claim 12 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

14. The apparatus of claim 11 wherein the first FAM and the second FAM are configured to operate simultaneously with respect to each other in the pipelined fashion such that the first FAM is configured to perform its operations with regard to financial market data while the second FAM performs its operations with regard to other financial market data.

15. The apparatus of claim 11 wherein the internal symbol IDs comprise a plurality of record keys for a plurality of financial instrument records corresponding to financial instruments associated with the received financial market data.

16. The apparatus of claim 1 wherein the firmware logic comprises a firmware socket module and a firmware application module pipeline;
wherein the firmware socket module is configured to (1) stream the financial market data into the reconfigurable logic device from the shared memory via the DMA transfers, and (2) provide the streaming financial market data to the firmware application module pipeline; and
wherein the firmware application module pipeline is configured to compute a plurality of VWAPs for a plurality of the financial instruments associated with the streaming financial market data that was provided to the firmware application module pipeline.

17. The apparatus of claim 16 wherein the firmware socket module is further configured to provide both command data and the streaming financial market data to the firmware application module pipeline, wherein the firmware application module pipeline is further configured arrange itself in accordance with the command data to control how the firmware application module operates.

18. The apparatus of claim 17 further comprising a bus, wherein the processor and the reconfigurable logic device are in communication with the bus, wherein the processor, bus, and reconfigurable logic device are part of a ticker plant, wherein the reconfigurable logic device is further configured to access the command data and the streaming financial market data via the bus, and wherein the processor is further config

Assignees

• Ip Reservoir Llc

Inventors

• Parsons Scott
• Taylor David E
• Schuehler David Vincent
• Franklin Mark A
• Chamberlain Roger D

Classifications

• G06Q40/00

  Finance; Insurance; Tax strategies; Processing of corporate or income taxes · CPC title

• G06Q40/06

  Asset management; Financial planning or analysis · CPC title

• G06Q40/04 Primary

  Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange · CPC title