Data-processing apparatus and data transfer control device

Patent metadata

Field	Value
Publication number	US-9672174-B2
Application number	US-201414289706-A
Country	US
Kind code	B2
Filing date	May 29, 2014
Priority date	Jun 10, 2013
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A data-processing apparatus includes: a plurality of processing blocks which is connected to a common bus; a memory which includes an address space having a plurality of banks; and a common bus arbitrating section which arbitrates an access request to access the memory, and controls data delivery through the common bus that receives the access request and is provided between the plurality of processing blocks and the memory. At least one processing block among the plural processing blocks is an exchange-processing block that performs exchange of an access order to access the banks in the memory when the communication of the data is performed between the memory and the processing block through the common bus. The exchange-processing block includes a data transfer control device that performs the exchange of the access order to access the banks by controlling the order of the data.

First claim

What is claimed is:

1. A data-processing apparatus comprising:
a plurality of processing blocks which are connected to a common bus;
a memory which includes an address space having a plurality of banks; and
a common bus arbitrating section which
arbitrates an access request to access the memory that is output from the plurality of processing blocks, and
controls data delivery through the common bus that receives the access request and is provided between the plurality of processing blocks and the memory,
wherein at least one processing block among the plurality of processing blocks includes a data transfer control device that exchanges bank accessing order to the memory for the same bank accessing order when another processing block access the memory, and wherein the data transfer control device accesses the banks in a reverse order to the order of the banks in the memory.

2. The data-processing apparatus according to claim 1 ,
wherein the data transfer control device includes:
a buffer section which stores the data that is transferred between the memory and the processing block;
a buffer write control section which stores the data in the buffer section; and
a buffer read control section which reads the data stored in the buffer section.

3. The data-processing apparatus according to claim 2 ,
wherein the data transfer control device further includes an operation mode register that sets the order of the data that is transferred between the memory and the processing block, and
the buffer write control section stores the data in storage regions of the buffer section corresponding to the banks based on the order of the data set by the operation mode register.

4. The data-processing apparatus according to claim 2 ,
wherein the data transfer control device further includes an operation mode register that sets the order of the data that is transferred between the memory and the processing block, and
the buffer read control section reads the data from storage regions of the buffer section corresponding to the banks based on the order of the data set in the operation mode register.

5. The data-processing apparatus according to claim 1 ,
wherein the data is data which has regions in a first direction and a second direction,
the data-processing apparatus further includes the plurality of exchange-processing blocks,
at least one exchange-processing block among the plurality of exchange-processing blocks accesses the banks in the memory in the first direction of the data, and
at least another exchange-processing block among the plurality of processing blocks that performs the exchange of the access order to the banks in the memory accesses the banks in the memory in the second direction of the data.

6. The data-processing apparatus according to claim 5 ,
wherein the data is image data,
the first direction is a horizontal direction of the image data, and
the second direction is a vertical direction of the image data.

7. A data transfer control device used for a data-processing apparatus including a plurality of processing blocks which is connected to a common bus; a memory which includes an address space having a plurality of banks; and a common bus arbitrating section which arbitrates an access request to access the memory that is output from the plurality of processing blocks, and controls data delivery through the common bus which receives the access request and is provided between the plurality of processing blocks and the memory,
wherein the data transfer control device is provided in at least one processing block among the plurality of processing blocks, and exchanges bank accessing order to the memory for the same bank accessing order when another processing block access the memory, and wherein the data transfer control device accesses the banks in a reverse order to the order of the banks in the memory.

Assignees

• Olympus Corp

Inventors

• Tanaka Yoshinobu
• Tomita Hironobu
• Ueno Akira

Classifications

• G06F13/30 Primary

  with priority control · CPC title

• G06F13/1673

  using buffers · CPC title

• G06F13/1626

  by reordering requests · CPC title