Processing of multiple instruction streams in a parallel slice processor

Patent metadata

Field	Value
Publication number	US-9672043-B2
Application number	US-201414274942-A
Country	US
Kind code	B2
Filing date	May 12, 2014
Priority date	May 12, 2014
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

Techniques for managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices provide flexibility in execution of program instructions by a processor core. An event is detected indicating that either resource requirement or resource availability will not be met by the execution slice currently executing the instruction stream. In response to detecting the event, dispatch of at least a portion of the subsequent instruction is made to another instruction execution slice. The event may be a compiler-inserted directive, may be an event detected by logic in the processor core, or may be determined by a thread sequencer. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution, ordinary instruction execution, wide instruction execution. When an instruction execution slice is busy processing a current instruction for one of the streams, another slice can be selected to proceed with execution.

First claim

What is claimed is:

1. A computer system comprising:
a processor for executing program instructions; and
a memory for storing the program instructions coupled to the processor; wherein the program instructions are program instructions for analyzing and modifying instructions of multiple instruction streams for further execution by another processor core having a plurality of instruction execution slices, and wherein the program instructions comprise:
program instructions for detecting, in a first one of the multiple instruction streams, an event indicating that a first instruction requires processing that changes resource availability for execution of a subsequent instruction of the first instruction stream or that the subsequent instruction has execution requirements such that a change in mapping between the instruction execution slices and corresponding ones of the multiple instruction streams is indicated, wherein the subsequent instruction is an instruction having a width greater than a width of each of the plurality of instruction execution slices, wherein the event is an SIMD instruction; and
program instructions for, responsive to detecting the event, modifying the first one of the multiple instruction streams by inserting a directive in the first one of the multiple instruction streams, wherein the directive, when executed by the another processor core will cause the change in mapping so that at least a portion of the subsequent instruction is dispatched to a selected one of the instruction execution slices that was assigned to a second one of the multiple instruction streams during a previous execution cycle, wherein the program instructions for inserting a directive insert a directive that causes dispatch of a first portion of the subsequent instruction to the selected instruction execution slice and a second portion of the subsequent instruction to another instruction execution slice that executed an instruction previous to the first instruction for the first instruction stream, wherein the program instructions for inserting a directive insert a directive that causes dispatch of the subsequent instruction to the selected instruction execution slice and another instruction execution slice that executed an instruction previous to the first instruction for the first instruction stream, wherein the selected instruction execution slice and the another instruction execution slice process different data associated with the SIMD instruction.

2. The computer system of claim 1 , wherein the program instructions for detecting an event predict that another instruction execution slice that executed a second instruction previous to the first instruction for the first instruction stream will be unavailable due to the second instruction being a complex instruction or an instruction having completion dependent on an external event.

3. The computer system of claim 1 , wherein the program instructions are program instructions of a compiler that generates program code of the multiple instruction streams by inserting the directive in the program code to control the dispatching.

4. The computer system of claim 1 , wherein the program instructions are program instructions of a scheduler that pre-processes program code of the multiple instruction streams to allocate resources to hardware threads corresponding to the multiple instruction streams.

5. A computer program product comprising a computer-readable storage device that is not a signal or carrier wave, the storage device storing program instructions for analyzing and modifying instructions of multiple instruction streams for execution by a processor core having a plurality of instruction execution slices, wherein the program instructions comprise:
program instructions for detecting, in a first one of the multiple instruction streams, an event indicating that a first instruction requires processing that changes resource availability or requirements for execution of a subsequent instruction of the first instruction stream such that a change in mapping between the instruction execution slices and corresponding ones of the multiple instruction streams is indicated, wherein the subsequent instruction is an instruction having a width greater than a width of each of the plurality of instruction execution slices; and
program instructions for, responsive to detecting the event, modifying the first one of the multiple instruction streams by inserting a directive in the first one of the multiple instruction streams, wherein the directive, when executed by the processor core will cause dispatch of at least a portion of the subsequent instruction to a selected one of the instruction execution slices that was assigned to a second one of the multiple instruction streams during a previous execution cycle, wherein the program instructions for inserting a directive insert a directive that causes dispatch of a first portion of the subsequent instruction to the selected instruction execution slice and a second portion of the subsequent instruction to another instruction execution slice that executed an instruction previous to the first instruction for the first instruction stream, wherein the event is an SIMD instruction and wherein the program instructions for inserting a directive insert a directive that causes dispatch of the subsequent instruction to the selected instruction execution slice and another instruction execution slice that executed an instruction previous to the first instruction for the first instruction stream, wherein the selected instruction execution slice and the another instruction execution slice process different data associated with the SIMD instruction.

6. The computer program product of claim 5 , wherein the program instructions for detecting an event predict that another instruction execution slice that executed a second instruction previous to the first instruction for the first instruction stream will be unavailable due to the second instruction being a complex instruction or an instruction having completion dependent on an external event.

7. The computer program product of claim 5 , wherein the program instructions are program instructions of a compiler that generates program code of the multiple instruction streams by inserting the directive in the program code to control the dispatching.

8. The computer program product of claim 5 , wherein the program instructions are program instructions of a scheduler that pre-processes program code of the multiple instruction streams to allocate resources to hardware threads corresponding to the instruction streams.

Assignees

• IBM

Inventors

• Eisen Lee Evan
• Le Hung Qui
• Leenstra Jentje
• Moreira Jose Eduardo
• Ronchetti Bruce Joseph
• Thompto Brian William
• Van Norstrand Jr Albert James

Classifications

• G06F9/30149

  of variable length instructions · CPC title

• G06F9/3867

  using instruction pipelines · CPC title

• G06F9/38 Primary

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title

• G06F9/3851 Primary

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title