Electro-optic display backplane structures with drive components and pixel electrodes on opposed surfaces

US9671635B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9671635-B2
Application numberUS-201514615617-A
CountryUS
Kind codeB2
Filing dateFeb 6, 2015
Priority dateFeb 7, 2014
Publication dateJun 6, 2017
Grant dateJun 6, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

This invention relates to an electro-optic display having a backplane with a front surface and a reverse surface on opposed sides of the backplane, a front surface having a plurality of pixel electrodes arranged in a matrix of columns and rows with column and row lines, a reverse surface having at least one driver chip, and conductive vias electrically connecting the column and row lines on the front surface to the driver chip on the reverse surface, such that the entire front surface area may be optically active.

First claim

Opening claim text (preview).

The invention claimed is: 1. An electro-optic display having a backplane, the backplane comprising: a substrate having a first major surface comprising a plurality of pixel electrodes arranged in an array of rows and columns having row and column lines, the pixel electrodes covering at least 95% of the first major surface; the substrate having a second major surface opposed to the first major surface, the second major surface having a first driver chip; and a first plurality of conductive vias electrically connecting the row lines of the pixel array through the substrate to the first driver chip. 2. The display of claim 1 further comprising a second plurality of conductive vias electrically connecting the column lines of the pixel array to the first driver chip. 3. The display of claim 1 further comprising: a second driver chip on the second major surface; and a plurality of second conductive vias electrically connecting the column lines of the pixel array to a second driver chip. 4. The display of claim 1 , wherein the backplane is a printed circuit board, a flex circuit, or a substrate of printed layers. 5. The display of claim 1 , wherein each of the plurality of pixel electrodes has a thin-film transistor associated therewith. 6. The display of claim 1 , wherein the pixel size is between 3 mm×3 mm and 5 mm×5 mm. 7. An assembly comprising a plurality of displays of claim 1 . 8. The assembly of claim 7 , wherein each of the plurality of displays is interconnected. 9. The assembly of claim 8 , wherein the assembly is configured to display a contiguous image across multiple displays.

Assignees

Inventors

Classifications

  • Combining plural substrates to produce large-area displays, e.g. tiled displays · CPC title

  • Arrangements for providing conduction through an insulating substrate · CPC title

  • for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

  • Conductors connecting driver circuitry and terminals of panels · CPC title

  • Integration of the drivers onto the display substrate · CPC title

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What does patent US9671635B2 cover?
This invention relates to an electro-optic display having a backplane with a front surface and a reverse surface on opposed sides of the backplane, a front surface having a plurality of pixel electrodes arranged in a matrix of columns and rows with column and row lines, a reverse surface having at least one driver chip, and conductive vias electrically connecting the column and row lines on the…
Who is the assignee on this patent?
E Ink Corp
What technology area does this patent fall under?
Primary CPC classification G02F1/13336. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 06 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).