Implementing hierarchical high radix switch with timesliced crossbar

Patent metadata

Field	Value
Publication number	US-9667564-B2
Application number	US-201314012055-A
Country	US
Kind code	B2
Filing date	Aug 28, 2013
Priority date	Aug 28, 2013
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A method and system are provided for implementing a hierarchical high radix switch with a time-sliced crossbar. The hierarchical high radix switch includes a plurality of inputs and a plurality of outputs. Each input belongs to one input group; each input group sends consolidated requests to each output, by ORing the requests from the local input ports in that input group. Each output port belongs to one output group; each output port grants one of the requesting input groups using a rotating priority defined by a next-to-serve pointer. Each output group consolidates the output port grants and allows one grant to pass back to an input group. Each input port in an input group evaluates all incoming grants in an oldest packet first manner to form an accept. Each input group consolidates the input port accepts and selects one accept to send to the output port.

First claim

What is claimed is:

1. A method for implementing hierarchical high radix switching with a time-sliced crossbar comprising:
providing a switching device comprising a plurality of inputs and a plurality of outputs; each input port belongs to one input group; and each output port belongs to one output group; providing a first respective link layer and data buffering logic block coupled to one said input group of said plurality of inputs; and providing a second respective link layer and data buffering logic block coupled to one said output group of said plurality of outputs; providing an arbitration element coupled to each said first respective link layer and data buffering logic block and coupled to each said second respective link layer and data buffering logic block; and providing a data crossbar coupled to each said first respective link layer and data buffering logic block and coupled to each said second respective link layer and data buffering logic block;
one said input port receiving a packet in its data queues for one said output port; and said input port requesting an output for one said output port;
each said input group, sending consolidated requests to each output by ORing the requests from the local input ports in said respective input group;
each said output port, granting one of the requesting input groups using a rotating priority defined by a next-to-serve pointer;
each said output group consolidating the output port grants and allowing one grant to pass back to one said input group;
each said input port in said input group evaluating all incoming grants in an oldest packet first manner to form an accept; and each said input group consolidating the input port accepts and selecting one accept to send to the output port;
providing said arbitration element with multiple input arbiters and multiple output arbiters; providing a separate arbitration path from a data path, each said input arbiter forming a request, queuing incoming packet destination information and managing active transfers; and each said output arbiter processing a grant, tracking subport availability and providing fairness using the next-to-serve pointer;
each said first respective link layer and data buffering logic block and each said second respective link layer and data buffering logic block managing link protocol, and handling sequencing an arbitration winning packet out to the data crossbar, and receiving incoming crossbar data to sequence to an output link; and
starting a data transfer, marking a time slice as busy, signaling data buffer logic and said data crossbar to start the packet data transfer, and transferring data in an assigned cycle once per supercycle and continuing data transfers until receiving an end of packet being signaled to guarantee all packet data is transferred; and marking the time slice as available.

2. The method as recited in claim 1 includes buffering incoming data at each said input port to create wide words to transmit through the time-sliced crossbar.

3. The method as recited in claim 1 includes providing an internal crossbar data width equal to k times the width of the incoming data stream, where k=the number of ports in an input/output group.

4. The method as recited in claim 1 includes at the output of the crossbar, serializing data from a wide word to a link width.

5. The method as recited in claim 1 wherein scheduling proceeds in a pipelined manner of request, grant, and accept, each occurring on consecutive clock cycles.

6. The method as recited in claim 1 includes providing one data transfer per packet per supercycle.

7. The method as recited in claim 1 includes providing packet store and forward or selectively providing packet cut through responsive to receiving valid header information.

8. The method as recited in claim 7 further includes enabling packet arbitration to start packet transfer.

9. A system for implementing a hierarchical high radix switch comprising:
a switching device comprising a wide timesliced access crossbar connected to a plurality of inputs and a plurality of outputs; each input port belongs to one input group; and each output port belongs to one output group;
a first respective link layer and data buffering logic block coupled to one said input group of said plurality of inputs; and a second respective link layer and data buffering logic block coupled to one said output group of said plurality of outputs;
an arbitration element coupled to each said first respective link layer and data buffering logic block and coupled to each said second respective link layer and data buffering logic block;
said data crossbar coupled to each said first respective link layer and data buffering logic block and coupled to each said second respective link layer and data buffering logic block;
said arbitration element including multiple input arbiters and multiple output arbiters and having a separate arbitration path from a data path; each said input arbiter forming a request, queuing incoming packet destination information and managing active transfers; and each said output arbiter processing a grant, tracking subport availability and providing fairness using the next-to-serve pointer;
each said first respective link layer and data buffering logic block and each said second respective link layer and data buffering logic block managing link protocol, and handling sequencing an arbitration winning packet out to the data crossbar, and receiving incoming crossbar data to sequence to an output link comprising;
one said input port receiving a packet in its data queues for one said output port; and said input port requesting an output for one said output port; each said input group, sending consolidated requests to each output by ORing the requests from the local input ports in said respective input group; each said output port, granting one of the requesting input groups using a rotating priority defined by a next-to-serve pointer; each said output group consolidating the output port grants and allowing one grant to pass back to one said input group; and each said input port in said input group evaluating all incoming grants in an oldest packet first manner to form an accept; and each said input group consolidating the input port accepts and selecting one accept to send to the output port; and
said arbitration element starting a packet data transfer, signaling data buffer logic and said data crossbar to start the packet data transfer, marking a time slice as busy, and transferring data per packet in an assigned cycle once per supercycle and continuing data transfers until an end of packet being signaled to guarantee all packet data is transferred; and marking the time slice as available.

10. The system as recited in claim 9 wherein said link layer and data buffering logic block buffers incoming data at an input port to create wide words to transmit through the wide timesliced access crossbar.

11. The system as recited in claim 9 wherein an internal crossbar data width equals k times the width of the incoming data stream, where k=the number of ports in an input/output group.

12. The system as recited in claim 9 wherein said link layer and data buffering logic block at the output of the crossbar serializes data from the wide word to the link width.

13. The system as recited in claim 9 wherein scheduling proceeds in a pipelined manner of request, grant, and accept, each occurring on consecutive clock cycles.

14. The system as recited in claim 13 wherein said arbiter provides one data transfer per packet per supercycle.

15. The system as recited in claim 9 wherein data transfer includes

Assignees

• IBM

Inventors

• Chrysos Nikolaos
• Kurup Girish G
• Minkenberg Cyriel J
• Pothireddy Anil
• Rudquist Mark L
• Srivastava Vibhor K
• Vanderpool Brian T

Classifications

• H04L49/3063

  Pipelined operation · CPC title

• H04L49/101 Primary

  using crossbar or matrix · CPC title