Semiconductor device

Patent metadata

Field	Value
Publication number	US-9667410-B2
Application number	US-201514844175-A
Country	US
Kind code	B2
Filing date	Sep 3, 2015
Priority date	Sep 5, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

In data processing including high-speed cipher calculation for which it is not appropriate to employ a leveling technique, tamper resistance is improved against an attack to a specific position performed by knowing a layout of functional blocks in a semiconductor chip. Examples of the attack include micro-probing, fault injection, and electromagnetic wave analysis.
A semiconductor device, in which a plurality of IC chips that perform the same cipher calculation in parallel are laminated or stacked, performs data processing including the cipher calculation. A chip that compares and verifies results of the cipher calculations performed by the plurality of chips is laminated in an intermediate layer whose element surface is covered by another chip. For example, when three chips are laminated, a chip in the intermediate layer sandwiched by the upper layer and the lower layer has a comparative verification function.

First claim

What is claimed is:

1. A semiconductor device in which a plurality of IC chips are laminated and which can perform data processing including cipher calculation,
wherein the IC chips perform a same cipher calculation in parallel and each IC chip calculates a calculation result, and
wherein an element surface of one IC chip of the IC chips is covered by another IC chip, and the one IC chip compares a plurality of calculation results corresponding to the IC chips with each other and controls content of subsequent data processing based on results of the comparison.

2. The semiconductor device according to claim 1 ,
wherein the one IC chip is laminated so that a surface opposite to the element surface is further covered by another IC chip.

3. The semiconductor device according to claim 2 ,
wherein when at least one of the calculation results is different from the other calculation results, the one IC chip starts processing corresponding to an attack.

4. The semiconductor device according to claim 2 ,
wherein when at least one calculation result of the calculation results is different from the other calculation results, the one IC chip causes an IC chip that outputs the different calculation result to perform recalculation of the cipher calculation,
wherein when a recalculation result is the same as the original calculation result, the one IC chip starts processing corresponding to a failure, and
wherein when the recalculation result is different from the original calculation result, the one IC chip starts processing corresponding to an attack.

5. The semiconductor device according to claim 2 ,
wherein when a calculation result of the one IC chip is different from the other calculation results, the one IC chip performs recalculation of the cipher calculation,
wherein when a recalculation result is the same as the original calculation result, the one IC chip starts processing corresponding to a failure,
wherein when the recalculation result is different from the original calculation result, the one IC chip starts processing corresponding to an attack, and
wherein among the calculation results, when a calculation result of at least one of the IC chips other than the one IC chip is different from the other calculation results, the one IC chip starts processing corresponding to an attack.

6. The semiconductor device according to claim 1 ,
wherein the IC chips have the same circuit configuration and an arrangement of a circuit that performs the cipher calculation is laid out at positions different from each other in plan view.

7. The semiconductor device according to claim 1 ,
wherein the IC chips have the same layout and are laminated in a state in which the IC chips are rotated by ±90° or 180° from each other, and/or element surfaces or substrate surfaces thereof face each other.

8. The semiconductor device according to claim 7 ,
wherein each of the IC chips has a plurality of terminals having functions respectively, and a terminal having the same function is arranged at least one position of a position rotated by ±90 ° or 180° around the same point and a symmetrical position with respect to a straight line in parallel with a side of the IC chip.

9. The semiconductor device according to claim 8 ,
wherein the terminals include a plurality of power supply terminals, a plurality of ground terminals, one or a plurality of data input/output terminals, one or a plurality of clock terminals, and one or a plurality of reset terminals.

10. The semiconductor device according to claim 1 ,
wherein each of the IC chips has an electrode penetrating through the substrate, and the electrodes are electrically coupled to each other.

11. A semiconductor device in which three IC chips, each of which has a TSV electrode penetrating through a substrate, are laminated,
wherein a second IC chip is laminated over a first IC chip with their TSV electrodes being coupled to each other and a third IC chip is laminated over the second IC chip with their TSV electrodes being coupled to each other, and
wherein each of the first, the second, and the third IC chips performs the same data processing and calculates a processing result of each IC chip, and the second IC chip compares processing results corresponding to the first, the second, and the third IC chips with each other, and controls content of subsequent data processing based on a result of the comparison.

12. The semiconductor device according to claim 11 ,
wherein at least two of the first, the second, and the third IC chips perform the aforementioned same data processing in parallel at a time.

13. The semiconductor device according to claim 12 ,
wherein the data processing is a part of a series of rounds where cipher processing is configured.

14. The semiconductor device according to claim 11 ,
wherein when the data processing is cipher processing, each of the first, the second, and the third IC chips performs the same cipher processing and calculates a processing result of each IC chip, and the second IC chip compares the processing results corresponding to the first, the second, and the third IC chips with each other, and
wherein when the data processing is other than cipher processing, the first, the second, and the third IC chips divide the data processing into different data processing portions and perform them in parallel.

15. A semiconductor device in which a plurality of IC chips are laminated and which can perform data processing including cipher calculation,
wherein among the IC chips, one IC chip in an intermediate layer, whose element surface is covered by another IC chip, is caused to perform processing that requires the highest tamper resistance in processing included in the data processing.

16. The semiconductor device according to claim 15 ,
wherein the IC chips perform the same cipher calculation in parallel and calculate calculation results respectively, and the IC chip in the intermediate layer compares the calculation results corresponding to the IC chips with each other, and controls content of subsequent data processing based on a result of the comparison.

17. The semiconductor device according to claim 15 ,
wherein the data processing includes the cipher calculation, the IC chip in the intermediate layer is caused to perform the cipher calculation, and the other IC chips are caused to perform other processing.

18. The semiconductor device according to claim 15 ,
wherein the data processing includes signature processing and certificate verification processing as the cipher calculation, the IC chip in the intermediate layer is caused to perform the signature processing, and the other IC chips are caused to perform other processing including the certificate verification processing.

19. The semiconductor device according to claim 15 ,
wherein a surface opposite to the element surface of the IC chip in the intermediate layer is further laminated with another IC chip so that the surface is covered by the other IC chip.

Assignees

• Renesas Electronics Corp

Inventors

• Oshida Daisuke

Classifications

• H04L9/003

  for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA] · CPC title

• H04L9/0631

  Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms · CPC title

• G06F21/554

  involving event detection and direct action · CPC title

• H04L2209/46

  Secure multiparty computation, e.g. millionaire problem · CPC title

• G06F21/71

  to assure secure computing or processing of information · CPC title