Ultrasound lens cleaner driver with frequency selectable oscillator

Patent metadata

Field	Value
Publication number	US-9667191-B2
Application number	US-201514799309-A
Country	US
Kind code	B2
Filing date	Jul 14, 2015
Priority date	Jul 14, 2015
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A frequency selectable driver circuit (driver circuit) includes a current drive transistor between a first and second node for driving a frequency selectable oscillator (FSO) coupled therebetween that includes a first LC network including an inductor L 2 and a capacitor C 2 in series and a second LC network in series with the first LC network. The second LC network includes a capacitor bank including capacitors in parallel including switches for switching (selectable capacitors) and an inductor L 3 in parallel to the capacitor bank. Values of L 2 and C 2 provide a low frequency point f L which the LC network is overall capacitive, and in a frequency range between f a and f b above f L with only a portion of selectable capacitors selected a capacitance of the capacitor bank and value of L 3 results in an overall impedance for the second LC network that is capacitive between f a and f b and inductive elsewhere.

First claim

The invention claimed is:

1. A frequency selectable driver circuit (driver circuit), comprising:
a current drive transistor coupled between a first node and a second node for driving a frequency selectable oscillator (FSO) coupled between said first node and said second node, said FSO including:
a first LC network comprising an inductor L 2 and a capacitor C 2 in series;
a second LC network in series with said first LC network comprising:
a capacitor bank including a plurality of capacitors in parallel including series switches for switching at least a portion of said plurality of capacitors (selectable capacitors), and
an inductor L 3 in parallel to said capacitor bank;
wherein values of said L 2 and said C 2 provide a low frequency point (f L ) which said first LC network has an overall impedance that is capacitive, and
wherein in a frequency range f a and f b above said f L with only a portion of said selectable capacitors selected in said capacitor bank, a value of capacitance of said capacitor bank and a value of said L 3 results in an overall impedance of said second LC network that is capacitive between said f a and f b and inductive elsewhere.

2. The driver circuit of claim 1 , wherein said second LC network comprises a parallel-resonant circuit.

3. The driver circuit of claim 1 , wherein a portion of said plurality of capacitors do not include said series switch.

4. The driver circuit of claim 1 , wherein said capacitor bank provides a switch configurable capacitance range of at least one order of magnitude.

5. The driver circuit of claim 1 , further comprising a substrate having a semiconductor surface that said driver circuit is formed on.

6. The driver circuit of claim 1 , wherein said current drive transistor comprises a bipolar transistor.

7. An integrated circuit (IC) combination, comprising:
a substrate having a semiconductor surface;
a processor on said semiconductor surface, and
a frequency selectable driver circuit (driver circuit) on said semiconductor surface comprising:
a current drive transistor coupled between a first node and a second node for driving a frequency selectable oscillator (FSO) coupled between said first node and said second node, said FSO including:
an first LC network comprising an inductor L 2 and a capacitor C 2 in series, and
a second LC network in series with said first LC network comprising:
a capacitor bank including a plurality of capacitors in parallel including series switches for switching at least a portion of said plurality of capacitors (selectable capacitors), and
an inductor L 3 in parallel to said capacitor bank;
wherein values of said L 2 and said C 2 provide a low frequency point (f L ) which said first LC network has an overall impedance that is capacitive;

wherein in a frequency range f a and f b above said f L with only a portion of said selectable capacitors selected in said capacitor bank, a value of capacitance of said capacitor bank and a value of said L 3 results in an overall impedance of said second LC network that is capacitive between said f a and f b , and inductive elsewhere, and
wherein said processor is coupled to said series switches of said capacitor bank for switching said selectable capacitors.

8. The IC combination of claim 7 , wherein said processor comprises a microcontroller unit (MCU).

9. The IC combination of claim 7 , wherein said second LC network comprises a parallel-resonant circuit.

10. The IC combination of claim 7 , wherein said capacitor bank provides a switch configurable capacitance range of at least one order of magnitude.

11. The IC combination of claim 7 , further comprising a memory associated with said processor on said semiconductor surface, wherein a lens module and transducer combination resonant frequencies profile and cleaning pattern algorithm is stored in said memory which includes code for adaptively changing a first cleaning pattern using feedback from an image quality measurement from an image generated by a camera system using said first cleaning pattern.

12. A camera system, comprising:
an IC combination on a substrate having a semiconductor surface, comprising:
a controller having an associated memory that stores a lens module and transducer combination resonant frequencies profile and cleaning pattern algorithm;
a frequency selectable driver circuit (driver circuit) having an input coupled to an output of said controller;
said driver circuit comprising:
a current drive transistor coupled between a first node and a second node for driving a frequency selectable oscillator (FSO) coupled between said first node and said second node, said FSO including:

a first LC network comprising an inductor L 2 and a capacitor C 2 in series,
a second LC network in series with said first LC network comprising:
a capacitor bank including a plurality of capacitors in parallel including series switches for switching at least a portion of said plurality of capacitors (selectable capacitors), and
an inductor L 3 in parallel to said capacitor bank;
wherein values of said L 2 and said C 2 provide a low frequency point (f L ) which said first LC network has an overall impedance that is capacitive, and
wherein in a frequency range f a and f b above said f L with only a portion of said selectable capacitors selected in said capacitor bank, a value of capacitance of said capacitor bank and a value of said L 3 results in an overall impedance of said second LC network that is capacitive between said f a and f b inductive elsewhere;
a transducer having at least one aperture having electrodes coupled to be driven by said driver circuit;
a lens module mechanically coupled to said transducer, and
a photodetector array opposite said lens module positioned for receiving light transmitted through said aperture.

13. The camera system of claim 12 wherein said transducer comprises a ring transducer.

14. The camera system of claim 12 , wherein said lens module and transducer combination resonant frequencies profile and cleaning pattern algorithm includes code for adaptively changing a first cleaning pattern using feedback from an image quality measurement from an image generated by said camera system using said first cleaning pattern.

15. The camera system of claim 12 , wherein said capacitor bank provides a switch configurable capacitance range of at least one order of magnitude.

Assignees

• Texas Instruments Inc

Inventors

• Li Yunhong
• Ma Wei

Classifications

• H04N23/51

  Housings · CPC title

• H04N23/811

  by dust removal, e.g. from surfaces of the image sensor or processing of the image signal output by the electronic image sensor · CPC title

• G02B27/0006

  with means to keep optical surfaces clean, e.g. by preventing or removing dirt, stains, contamination, condensation (G02B1/18 takes precedence; cleaning in general B08B) · CPC title

• H04N5/2254

  Electricity · mapped topic

• H03B5/1203 Primary

  the amplifier being a single transistor · CPC title