Nitride-based transistors with a cap layer and a recessed gate

Patent metadata

Field	Value
Publication number	US-9666707-B2
Application number	US-68591010-A
Country	US
Kind code	B2
Filing date	Jan 12, 2010
Priority date	Jul 23, 2004
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

An anneal of a gate recess prior to formation of a gate contact, such as a Schottky contact, may reduce gate leakage and/or provide a high quality gate contact in a semiconductor device, such as a transistor. The use of an encapsulation layer during the anneal may further reduce damage to the semiconductor in the gate recess of the transistor. The anneal may be provided, for example, by an anneal of ohmic contacts of the device. Thus, high quality gate and ohmic contacts may be provided with reduced degradation of the gate region that may result from providing a recessed gate structure as a result of etch damage in forming the recess.

First claim

That which is claimed is:

1. A high electron mobility transistor (HEMT), comprising:
a barrier layer;
a cap layer on the barrier layer;
a gate recess in the cap layer that extends to, but not through, the barrier layer;
a gate contact in the gate recess, wherein a sheet resistance of the barrier layer proximate the gate recess is substantially the same after an anneal of the barrier layer, the cap layer and the gate recess as an as grown sheet resistance of the barrier layer; and
an encapsulation layer in the gate recess conformally on sidewalls of the gate recess and not on an upper surface of the cap layer, a top surface of the encapsulation layer being co-planar with a top surface of the cap layer, the encapsulation layer extending between the gate contact and the cap layer such that the gate contact is spaced apart from a surface of the barrier layer opposite an upper surface of the gate contact and the gate contact is directly on an entire surface of the encapsulation layer in the gate recess.

2. The HEMT of claim 1 , further comprising ohmic contact material patterns in ohmic contact recesses in the cap layer, wherein the ohmic contact material patterns are annealed with the barrier layer, the cap layer and the gate recess.

3. The HEMT of claim 2 , further comprising a channel layer, wherein the barrier layer is on the channel layer and wherein the channel layer is annealed with the barrier layer, the ohmic contact material patterns, the cap layer and the gate recess.

4. The HEMT of claim 1 , wherein the gate contact comprises a Schottky contact.

5. The HEMT of claim 1 , wherein the cap layer comprises a GaN layer on the barrier layer.

6. The HEMT of claim 1 , wherein the cap layer comprises:
a GaN layer on the barrier layer; and
a SiN layer on the GaN layer.

7. The HEMT of claim 6 , wherein the SiN layer is formed in-situ.

8. The HEMT of claim 1 , wherein the gate recess extends through the cap layer and into but not through the barrier layer.

9. The HEMT of claim 1 , wherein the cap layer comprises a GaN based semiconductor material.

10. The HEMT of claim 1 , wherein the cap layer is directly on the barrier layer.

11. The HEMT of claim 1 , wherein the encapsulation layer comprises one of aluminum nitride (AlN) and an inert ceramic material.

12. A high electron mobility transistor (HEMT), comprising:
a barrier layer;
a cap layer on the barrier layer;
a gate recess in the cap layer that extends to, but not through, the barrier layer;
a gate contact in the gate recess, wherein a sheet resistance of the barrier layer proximate the gate recess is substantially the same after an anneal of the barrier layer, the cap layer and the gate recess as an as grown sheet resistance of the barrier layer; and
a protective layer in the gate recess, a top surface of the protective layer being co-planar with a top surface of the cap layer, the protective layer extending between the gate contact and the cap layer such that a surface of the barrier layer opposite an upper surface of the gate contact is spaced apart from the gate contact and that the gate contact is directly on an entire surface of the protective layer in the gate recess,
wherein the protective layer comprises one or more layers including at least one of silicon nitride (SiN), aluminum nitride (AlN), silicon oxide (SiO 2 ), and an oxide-nitride-oxide (ONO) structure.

13. The HEMT of claim 12 , wherein the protective layer extends on a surface of the cap layer opposite the barrier layer.

14. The HEMT of claim 13 , wherein the protective layer extends on sidewalls of the cap layer adjacent ohmic contacts of the HEMT.

Assignees

• Sheppard Scott
• Smith Richard Peter
• Cree Inc

Inventors

• Sheppard Scott
• Smith Richard Peter

Classifications

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H01L29/7787 Primary

  Electricity · mapped topic

• H01L29/778

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic