Method of manufacturing a semiconductor device including a gate electrode on a protruding group III-V material layer

Patent metadata

Field	Value
Publication number	US-9666706-B2
Application number	US-201615210368-A
Country	US
Kind code	B2
Filing date	Jul 14, 2016
Priority date	Nov 15, 2011
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a group III-V material layer comprising a protruded portion on substrate;
forming a barrier layer covering the protruded portion of the group III-V material layer, the barrier layer being a group III-V compound layer;
forming a gate insulation film on the barrier layer;
forming a gate electrode on the gate insulation film; and
forming source and drain electrodes spaced apart from the gate electrode,
wherein the protruded portion of the group III-V material layer is substantially defect-free.

2. The method of claim 1 , wherein the forming the group III-V material layer comprising a protruded portion on substrate comprises:
forming the group III-V material layer on the substrate; and
forming an insulating layer surrounding a portion of the III-V material layer that is not protruded.

3. The method of claim 1 , wherein the barrier layer has a bandgap larger than a bandgap of the group III-V material layer.

4. The method of claim 1 , wherein the barrier layer comprises a group III-V material for forming a quantum well.

5. The method of claim 1 , wherein the source and drain electrodes are formed to contact the barrier layer and the gate insulation film.

6. The method of claim 1 , wherein the group III-V material layer and the barrier layer are formed by using an epitaxy method.

7. The method of claim 1 , wherein the group III-V material layer and the barrier layer are continuous with one another.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Young-Jin
• Kim Kyoung-Yeon
• Lee Sang-Moon
• Hong Ki-Ha
• Hwang Eui-Chul

Classifications

• H10P14/3414

  being group IIIA-VIA materials · CPC title

• H10P10/00

  Bonding of wafers, substrates or parts of devices · CPC title

• H01L21/02538

  Electricity · mapped topic

• H01L29/66431

  Electricity · mapped topic

• H01L29/122

  Electricity · mapped topic