Memory devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9666592-B2
Application number	US-201514861262-A
Country	US
Kind code	B2
Filing date	Sep 22, 2015
Priority date	Sep 29, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A memory device includes a substrate having common source regions thereon, common source lines extending along a surface of the substrate and contacting the common source regions, respectively, and channel structures extending away from the surface of the substrate between the common source lines. The common source lines define a unit cell of the memory device therebetween. The memory device further includes an electrode stack structure having interlayer insulating layers and conductive electrode layers that are alternately stacked along sidewalls of the channel structures. The conductive electrode layers define respective gates of selection transistors and memory cell transistors of the memory device. An isolation insulating layer, which includes a portion of a sacrificial layer, is disposed between adjacent ones of the interlayer insulating layers in the stack structure. The isolation insulating layer divides at least one of the conductive electrode layers in the stack structure into electrically separate portions.

First claim

What is claimed is:

1. A memory device, comprising:
a substrate;
a cell region including at least one ground select transistor, at least one string select transistor, and a plurality of memory cell transistors, defined by respective gate electrode layers stacked on the substrate;
a plurality of isolation areas dividing the cell region into a plurality of unit cell regions; and
at least one isolation insulating layer disposed parallel to an upper surface of the substrate between directly adjacent ones of the isolation areas, and dividing at least one of the respective gate electrode layers that define the at least one ground select transistor in the plurality of unit cell regions,
wherein ones of the respective gate electrode layers that define the plurality of memory cell transistors are not divided by the at least one isolation insulating layer in the plurality of unit cell regions.

2. A memory device, comprising:
a substrate;
a cell region including at least one ground select transistor, at least one string select transistor, and a plurality of memory cell transistors, defined by respective gate electrode layers stacked on the substrate;
a plurality of isolation areas dividing the cell region into a plurality of unit cell regions;
at least one isolation insulating layer disposed parallel to an upper surface of the substrate between directly adjacent ones of the isolation areas, and dividing at least one of the respective gate electrode layers that define the at least one ground select transistor in the plurality of unit cell regions; and
a gate isolation layer dividing at least one of the respective gate electrode layers that define the at least one string select transistor,
wherein the at least one of the respective gate electrode layers that define the at least one string select transistor and the ones of the respective gate electrode layers that define the plurality of memory cell transistors are not divided by the at least one isolation insulating layer.

3. A memory device, comprising:
a substrate including common source regions thereon;
common source lines extending along a surface of the substrate and contacting the common source regions, respectively, wherein adjacent ones of the common source lines define a unit cell of the memory device therebetween;
channel structures on the substrate between the adjacent ones of the common source lines, wherein the channel structures extend away from the surface of the substrate;
an electrode stack structure including interlayer insulating layers and conductive electrode layers that are alternately stacked along sidewalls of the channel structures, wherein the conductive electrode layers define respective gates of selection transistors and memory cell transistors of the memory device; and
an isolation insulating layer comprising a portion of a sacrificial layer that is disposed between adjacent ones of the interlayer insulating layers in the stack structure, wherein the portion of the sacrificial layer defining the isolation insulating layer comprises a material having a lower etching rate than other sacrificial layers used in the stack structure,
wherein the isolation insulating layer divides at least one of the conductive electrode layers in the stack structure into electrically separate portions.

4. The memory device of claim 3 , wherein the at least one of the conductive electrode layers, which is divided by the isolation insulating layer, defines a gate of at least one of the selection transistors of the memory device.

5. The memory device of claim 4 , wherein the at least one of the selection transistors comprises a ground select transistor, and further comprising:
a gate isolation layer that divides one or more of the conductive electrode layers in the stack structure into electrically separate portions,
wherein the one or more of the conductive electrode layers define respective gates of one or more string select transistors, and wherein the gate isolation layer comprises a same material as the interlayer insulating layers in the stack structure.

6. The memory device of claim 4 , wherein upper and lower ones of the interlayer insulating layers in the stack structure have different thicknesses than ones of the interlayer insulating layers therebetween in the stack structure.

7. A memory device, comprising:
a substrate;
a cell region including at least one ground select transistor, at least one string select transistor, and a plurality of memory cell transistors, defined by respective gate electrode layers stacked on the substrate;
a plurality of isolation areas dividing the cell region into a plurality of unit cell regions; and
at least one isolation insulating layer disposed parallel to an upper surface of the substrate between directly adjacent ones of the isolation areas, and dividing at least one of the respective gate electrode layers that define the at least one ground select transistor in the plurality of unit cell regions,
wherein the at least one isolation insulating layer is confined between respective interlayer insulating layers thereabove and therebelow, wherein the respective interlayer insulating layers are alternatingly stacked between the respective gate electrode layers on the substrate.

Assignees

• Yun Tae Hwan
• Lee Joon Hee
• Kim Ji Young
• Samsung Electronics Co Ltd

Inventors

• Yun Tae Hwan
• Lee Joon Hee
• Kim Ji Young

Classifications

• H01L27/11582

  Electricity · mapped topic

• H01L21/8229

  Electricity · mapped topic

• H01L27/1157 Primary

  Electricity · mapped topic

• H01L21/8221

  Electricity · mapped topic

• H10D88/01

  Manufacture or treatment · CPC title