Package-on-package structures

Patent metadata

Field	Value
Publication number	US-9666571-B2
Application number	US-201514960794-A
Country	US
Kind code	B2
Filing date	Dec 7, 2015
Priority date	Aug 19, 2011
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

First claim

What is claimed is:

1. A method for forming a package on package arrangement, the method comprising:
forming a first package, wherein forming the first package comprises
forming a substrate layer that includes (i) a top side, and (ii) a bottom side that is opposite to the top side, wherein the top side of the substrate layer defines a substantially flat surface,
coupling a die to the bottom side of the substrate layer,
covering the die using an encapsulant,
forming a ball grid array (BGA) of first solder balls in recesses of the encapsulant, and
forming second solder balls, wherein each of the second solder balls is melted by a non-weld process to a corresponding one of the first solder balls in the recesses of the encapsulant, wherein the second solder balls (i) are partially in the recesses of the encapsulant and (ii) partially protrude beyond the encapsulant, wherein the portion of the second solder balls that protrudes beyond the encapsulant is substantially spherical, smooth, and void of any sharp features;

forming a second package, wherein forming the second package comprises
forming a plurality of rows of third solder balls that extend (i) across the substantially flat surface of the top side of the substrate layer of the first package and (ii) over the die coupled to the bottom side of the substrate layer of the first package;

attaching the second package, via the plurality of rows of third solder balls, to the substantially flat surface of the top side of the substrate layer of the first package;
attaching fourth solder balls to the bottom side of the substrate layer and a top side of the die; and
forming a plurality of through-silicon vias in the die, wherein the plurality of through-silicon vias respectively extend between (i) at least some of the fourth solder balls and (ii) a plurality of fifth solder balls that are attached to a bottom side of the bottom package.

2. The method of claim 1 , wherein coupling the die to the bottom side of the substrate layer comprises:
attaching, using an adhesive layer located between the die and the substrate layer, the die to the bottom side of the substrate layer of the first package.

3. The method of claim 1 , further comprising:
forming a bond pad on the bottom side of the die;
forming a substrate pad on the bottom side of the substrate layer of the first package; and
coupling the bond pad of the die, via a wire, to the substrate pad of the substrate layer to route electrical signals of the die.

4. The method of claim 1 , wherein the substrate layer comprises a first substrate layer, and wherein forming the second package further comprises:
arranging, within the second package, a first die next to a second die, wherein each of the first die and the second die is connected to a second substrate layer in the second package via fourth solder balls.

5. The method of claim 4 , wherein at least some of the plurality of rows of third solder balls are between (i) the first die and the second die of the second package and (ii) the die coupled to the bottom side of the substrate layer.

6. The method of claim 1 , further comprising:
attaching thermal interface material to a bottom side of the die.

7. The method of claim 6 , further comprising:
attaching thermal conductive material to the thermal interface material.

8. The method of claim 6 , wherein the thermal interface material comprises one of a film, a grease composition, or an underfill material.

9. A method for forming a stackable semiconductor package, the method comprising:
forming a first package, wherein forming the first package comprises
forming a substrate layer including (i) a top side, and (ii) a bottom side that is opposite to the top side, wherein the top side of the substrate layer defines a substantially flat surface,
coupling a die to the bottom side of the substrate layer,
covering, using an encapsulant, the die,
forming a ball grid array (BGA) of first solder balls in recesses of the encapsulant,
forming second solder balls, wherein individual ones of the second solder balls is melted to a corresponding one of the first solder balls in the recesses of the encapsulant, wherein the second solder balls (i) are partially in the recesses of the encapsulant and (ii) partially protrude beyond the encapsulant by a first distance, and
forming third solder balls that are (i) electrically connected to the die via an interposer and (ii) protruding beyond the encapsulant by a second distance equal to the first distance;

forming a second package, wherein forming the second package comprises
forming a plurality of rows of fourth solder balls that extend (i) across the substantially flat surface of the top side of the substrate layer of the first package and (ii) over the die coupled to the bottom side of the substrate layer of the first package;

attaching the second package, via the plurality of rows of fourth solder balls, to the substantially flat surface of the top side of the substrate layer of the first package;
attaching third solder balls to the bottom side of the substrate layer and a top side of the die; and
forming a plurality of through-silicon vias in the die, wherein the plurality of through-silicon vias respectively extend between at least some of the third solder balls, and a plurality of fourth solder balls that are attached to a bottom side of the bottom package.

10. The method of claim 9 , further comprising:
attaching, using an adhesive layer located between the die and the substrate layer, the die to the bottom side of the substrate layer of the first package.

11. The method of claim 10 , further comprising:
attaching a printed circuit board to a bottom side of the die.

12. The method of claim 9 , further comprising:
forming a bond pad on the bottom side of the die;
forming a substrate pad on the bottom side of the substrate layer of the first package; and
coupling, via a wire, the bond pad of the die to the substrate pad of the substrate layer to route electrical signals of the die.

13. The method of claim 9 , wherein the substrate layer comprises a first substrate layer, and wherein forming the second package further comprises:
arranging, within the second package, a first die next to a second die, wherein each of the first die and the second die is connected to a second substrate layer in the second package via fifth solder balls.

14. The method of claim 9 , further comprising:
attaching thermal interface material to a bottom side of the die.

15. The method of claim 14 , further comprising:
attaching thermal conductive material to the thermal interface material.

16. The method of claim 14 , wherein the thermal interface material comprises one of a film, a grease composition, or an underfill material.

17. The method of claim 9 , further comprising:
attaching fifth solder balls to the bottom side of the substrate layer and a top side of the die.

Assignees

• Marvell World Trade Ltd

Inventors

• Kao Huahung
• Liou Shiann-Ming

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title