DIMM SSD SoC DRAM byte lane skewing

Patent metadata

Field	Value
Publication number	US-9666263-B2
Application number	US-201514973720-A
Country	US
Kind code	B2
Filing date	Dec 17, 2015
Priority date	Oct 7, 2015
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

A Dual In-Line Memory Module (DIMM) Solid State Drive (SSD) System-on-a-Chip (SoC) ( 345 ) is disclosed. The DIMM SSD SoC ( 345 ) can interoperate with a host memory controller ( 335 ) as though it were a traditional Dynamic Random Access Memory (DRAM) DIMM ( 105, 130 ) with system interconnect skew and on-DIMM skew, even though the DIMM SSD SoC ( 345 ) does not have on-DIMM skew. The DIMM SSD SoC ( 345 ) can include variable delay elements ( 422, 424, 426, 428, 430, 432, 434, 436, 438 ) that can replicate the delay a traditional DRAM DIMM ( 105, 130 ) experiences and that the host memory controller ( 335 ) expects, or a superior delay that minimizes system signal integrity issues, thereby increasing maximum system speed.

First claim

What is claimed is:

1. A Dual In-Line Memory Module (DIMM) Solid State Drive (SSD) System-on-a-Chip (SoC), comprising:
a controller chip;
a first interface to transmit signals between a host processor and the controller chip;
a plurality of data groups, each data group capable of storing a portion of information for a group;
a second interface to transmit information between the host processor and the plurality of data groups;
a plurality of variable delay elements;
first circuitry connecting the controller chip to each of the plurality of variable delay elements; and
second circuitry to connect each of the plurality of variable delay elements with one of the plurality of data groups,
wherein each of the plurality of variable delay elements is configured to reproduce a chosen skew delay representative of a Fly-By DIMM topology, and
wherein the chosen skew delay is determined by probing a Dual In-Line Memory Module (DIMM).

2. A DIMM SSD SoC according to claim 1 , wherein:
the group includes a byte of information; and
the plurality of data groups simulates a x8 DRAM construction.

3. A DIMM SSD SoC according to claim 1 , wherein:
the group includes a nibble of information; and
the plurality of data groups simulates a x4 DRAM construction.

4. A DIMM SSD SoC according to claim 1 , wherein the plurality of variable delay elements may be statically configured to reproduce the chosen skew delay.

5. A DIMM SSD SoC according to claim 1 , wherein the plurality of variable delay elements may be dynamically configured to reproduce the chosen skew delay.

6. A DIMM SSD SoC according to claim 1 , wherein the plurality of variable delay elements delay a clock signal to the plurality of data groups.

7. A DIMM SSD SoC according to claim 6 , wherein the plurality of data groups may receive staggered clock signals from the plurality of variable delay elements.

8. A DIMM SSD SoC according to claim 1 , wherein the plurality of variable delay elements may delay a transmit signal to the plurality of data groups.

9. A DIMM SSD SoC according to claim 8 , wherein the plurality of data groups may receive staggered transmit signals from the plurality of variable delay elements.

10. A method, comprising:
probing a Dual In-Line Memory Module (DIMM)
to determine a plurality of delays in the DIMM associated with lanes in a group; and
structuring a DIMM Solid State Drive (SSD) System-on-a-Chip (SoC) with the plurality of delays to simulate the DIMM using the DIMM SSD SoC.

11. A method according to claim 10 , wherein structuring a DIMM SSD SoC with the plurality of delays includes structuring the DIMM SSD SoC to reproduce the plurality of delays on a plurality of data groups in the group.

12. A method according to claim 10 , wherein structuring the DIMM SSD SoC to reproduce the plurality of delays on a plurality of data groups in the group includes programming a delay duration for each of the plurality of delays in a one of plurality of variable delay elements, each of the plurality of variable delay elements connected to one of the plurality of data groups.

13. A method according to claim 11 , wherein structuring the DIMM SSD SoC to reproduce the plurality of delays on a plurality of data groups in the group includes structuring the DIMM SSD SoC to reproduce the plurality of delays on a plurality of clock signals, each of the plurality of clock signals going to one data group.

14. A method according to claim 13 , wherein structuring the DIMM SSD SoC to reproduce the plurality of delays on a plurality of clock signals includes structuring the DIMM SSD SoC to stagger the plurality of clock signals to the plurality of data groups.

15. A method according to claim 11 , wherein structuring the DIMM SSD SoC to reproduce the plurality of delays on a plurality of data groups in the group includes structuring the DIMM SSD SoC to reproduce the plurality of delays on a plurality of transmit signals, each of the plurality of clock signals going to one data group.

16. A method according to claim 15 , wherein structuring the DIMM SSD SoC to reproduce the plurality of delays on a plurality of data groups in the group includes structuring the DIMM SSD SoC to stagger the plurality of transmit signals to the plurality of data groups.

Assignees

• Hanson Craig
• Samsung Electronics Co Ltd

Inventors

• Hanson Craig

Classifications

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C16/32

  Timing circuits · CPC title

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G11C11/4076 Primary

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title