Shift register unit, gate driving circuit and display device

Patent metadata

Field	Value
Publication number	US-9666152-B2
Application number	US-201314235957-A
Country	US
Kind code	B2
Filing date	Jun 19, 2013
Priority date	Mar 29, 2013
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

Provided are a shift register unit, a gate driving circuit and a display device, wherein the shift register unit includes: a pull-up module connected to a clock signal line and a signal output terminal; at least two pull-down modules both connected to a low level signal line and the signal output terminal; a control module connected to the pull-up module and the pull-down modules, for controlling the pull-up module to be turned on, so that the pull-up module outputs a high level signal input from the clock signal line to the signal output terminal, and for controlling the at least two pull-down modules to be turned on alternatively, so that the at least two pull-down modules output a low level signal input from the low level signal line to the signal output terminal, and for controlling one of the at least two pull-down modules to be turned on while controlling the other pull-down modules of the at least two pull-down modules to be discharged. The shift register unit can reduce over-bias of a gate of a pull-down TFT effectively, thus improving stability of the shift register unit.

First claim

What is claimed is:

1. A shift register unit, comprising:
a pull-up module connected to a clock signal line and a signal output terminal;
at least two pull-down modules both connected to a low level signal line and the signal output terminal;
a control module connected to the pull-up module and the at least two pull-down modules, for controlling the pull-up module to be turned on, so that a high level signal input from the clock signal line is output to the signal output terminal, and for controlling the at least two pull-down modules to be turned on alternatively, so that a low level signal input from the low level signal line is output to the signal output terminal, and for controlling one of the at least two pull-down modules to be turned on while controlling the other pull-down modules of the at least two pull-down modules to be discharged,
wherein the at least two pull-down modules comprise a first TFT and a second TFT, and the control module comprises a third TFT and a fourth TFT; and
wherein a gate of the third TFT is connected to a gate of the first TFT, a drain of the third TFT is connected to a gate of the second TFT, and a source of the third TFT is connected to the low level signal line; a gate of the fourth TFT is connected to the gate of the second TFT, a drain of the fourth TFT is connected to the gate of the first TFT, and a source of the fourth TFT is connected to the low level signal line.

2. The shift register unit of claim 1 , wherein drains of the first TFT and the second TFT are both connected to the signal output terminal, sources thereof are both connected to the low level signal line, the gate of the first TFT is connected to a first signal line, and the gate of the second TFT is connected to a second signal line, and a signal input from the first signal line and a signal input from the second signal line are level signals with inverted amplitudes.

3. The shift register unit of claim 2 , wherein the control module further comprises a scan control sub-module, and the pull-up module comprises a fifth TFT and a capacitor, wherein a gate of the fifth TFT is connected to the scan control sub-module, a drain of the fifth TFT is connected to the clock signal line, and a source of the fifth TFT is connected to the signal output terminal; one terminal of the capacitor is connected to the gate of the fifth TFT, and the other terminal of the capacitor is connected to the drains of the first TFT and the second TFT.

4. The shift register unit of claim 3 , wherein the control module comprises a sixth TFT, wherein a gate of the sixth TFT is connected to the gate of the first TFT, a drain of the sixth TFT is connected to the gate of the fifth TFT, and a source of the sixth TFT is connected to the low level signal line.

5. The shift register unit of claim 3 , wherein the control module further comprises a seventh TFT, wherein a gate of the seventh TFT is connected to the gate of the second TFT, a drain of the seventh TFT is connected to the gate of the fifth TFT, and a source of the seventh TFT is connected to the low level signal line.

6. A gate driving circuit, comprising a plurality of shift registers units of claim 1 connected in cascade.

7. The gate driving circuit of claim 6 , wherein the at least two pull-down modules comprise a first TFT and a second TFT, wherein drains of the first TFT and the second TFT are both connected to the signal output terminal, sources thereof are both connected to the low level signal line, a gate of the first TFT is connected to a first signal line, and a gate of the second TFT is connected to a second signal line, and a signal input from the first signal line and a signal input from the second signal line are level signals with inverted amplitudes.

8. The gate driving circuit of claim 7 , wherein,
in a case where the shift register unit is an odd-numbered stage of shift register unit, the gate of the first TFT therein is connected to the gate of the second TFT in a next stage of shift register unit, the gate of the second TFT therein is connected to the gate of the first TFT in the next stage of shift register unit;
in a case where the shift register unit is an even-numbered stage of shift register unit, the gate of the first TFT therein is connected to the gate of the second TFT in a previous stage of shift register unit, the gate of the second TFT therein is connected to the gate of the first TFT in the previous stage of shift register unit; the gate of the first TFT in the odd-numbered stage of shift register unit is connected to the first signal line, and the gate of the first TFT in the even-numbered stage of shift register unit is connected to the second signal line.

9. The gate driving circuit of claim 7 , wherein the control module comprises a third TFT and a fourth TFT, wherein a gate of the third TFT is connected to the gate of the first TFT, a drain of the third TFT is connected to the gate of the second TFT, and a source of the third TFT is connected to the low level signal line; a gate of the fourth TFT is connected to the gate of the second TFT, a drain of the fourth TFT is connected to the gate of the first TFT, and a source of the fourth TFT is connected to the low level signal line; and
the control module further comprises a scan control sub-module, and the pull-up module comprises a fifth TFT and a capacitor, wherein a gate of the fifth TFT is connected to the scan control sub-module, a drain of the fifth TFT is connected to the clock signal line, and a source of the fifth TFT is connected to the signal output terminal; one terminal of the capacitor is connected to the gate of the fifth TFT, and the other terminal of the capacitor is connected to the drains of the first TFT and the second TFT.

10. The gate driving circuit of claim 9 , wherein the scan control sub-module comprises an eighth TFT and a ninth TFT;
in the case where the shift register unit is an odd-numbered stage of shift register unit, a gate of the eighth TFT is connected to a signal output terminal of a previous odd-numbered stage of shift register unit, a drain of the eighth TFT is connected to a forward scan control signal line, and a source of the eighth TFT is connected to the gate of the fifth TFT, a gate of the ninth TFT is connected to a signal output terminal of a next odd-numbered stage of shift register unit, a drain of the ninth TFT is connected to a backward scan control signal line, and a source of the ninth TFT is connected to the gate of the fifth TFT;
in the case where the shift register unit is an even-numbered stage of shift register unit, the gate of the eighth TFT is connected to a signal output terminal of a previous even-numbered stage of shift register unit, the drain of the eighth TFT is connected to the forward scan control signal line, and the source of the eighth TFT is connected to the gate of the fifth TFT, the gate of the ninth TFT is connected to a signal output terminal of a next even-numbered stage of shift register unit, the drain of the ninth TFT is connected to the backward scan control signal line, and the source of the ninth TFT is connected to the gate of the fifth TFT.

11. The gate driving circuit of claim 9 , wherein the shift register unit further comprises a thirteenth TFT and a fourteenth TFT;
in the case where the shift register unit is an odd-numbered stage of shift register unit, gates of the thirteenth TFT and the fourteenth TFT are both connected to the gate of the fifth TFT in a previous stage of shift register unit, and sources of the thirteenth TFT and the fourteenth TFT are both connected to the low level signal line, a drain of the thirteenth TFT is connected to the gate of the first TFT in the present stage of shift regi

Assignees

• Hefei Boe Optoelectronics Tech
• Boe Technology Group Co Ltd

Inventors

• Hu Zuquan
• Wang Guolei
• Ma Rui
• Hu Ming

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0283

  Arrangement of drivers for different directions of scanning · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title