Amplifying circuit

Patent metadata

Field	Value
Publication number	US-9666143-B2
Application number	US-201514855376-A
Country	US
Kind code	B2
Filing date	Sep 15, 2015
Priority date	Sep 16, 2014
Publication date	May 30, 2017
Grant date	May 30, 2017

Abstract

An amplifying circuit includes a first differential amplifier (first differential pair) and a second differential amplifier (second differential pair) having an input capacitance smaller than the first differential amplifier. The amplifying circuit switches between the first differential amplifier (first differential pair) and the second differential amplifier (second differential pair) in response to an amplification mode setting signal to perform amplification processing of an input signal.

First claim

What is claimed is:

1. An amplifying circuit for amplifying an input signal applied thereto through its input line, and for outputting the amplified signal through its output line, the amplifying circuit comprising:
a first differential amplifier;
a second differential amplifier having an input capacitance larger than the first differential amplifier; and
an amplifier switch unit for outputting, through the output line, a signal caused by amplification of the input signal in the first differential amplifier in response to an amplification mode setting signal indicative of a high speed mode, and for outputting, through the output line, a signal caused by amplification of the input signal in the second differential amplifier, in response to the amplification mode setting signal indicative of a small offset mode.

2. The amplifying circuit according to claim 1 , further comprising a control unit for generating the amplification mode setting signal indicative of the high speed mode only during a period from transition start time at which a level of the input signal starts to increase or decrease until the level of the input signal becomes constant, and for generating the amplification mode setting signal indicative of the small offset mode in other periods.

3. The amplifying circuit according to claim 1 , wherein
the input line is connected to an input terminal of the first differential amplifier and the output line is connected to an output terminal of the first differential amplifier, and
the amplifier switch unit connects the input line to an input terminal of the second differential amplifier while connecting an output terminal of the second differential amplifier to the output line when the amplification mode setting signal indicates the small offset mode, whereas the amplifier switch unit connects the output line to the input terminal of the second differential amplifier, while blocking the connection between the output line and the output terminal of the second differential amplifier when the amplification mode setting signal indicates the high speed mode.

4. The amplifying circuit according to claim 3 , wherein
the amplifier switch unit includes:
a first switch for connecting the input line to the input terminal of the second differential amplifier when the amplification mode setting signal indicates the small offset mode, and for connecting the output line to the input terminal of the second differential amplifier when the amplification mode setting signal indicates the high speed mode, and
a second switch for connecting the output line to the output terminal of the second differential amplifier when the amplification mode setting signal indicates the small offset mode, and for blocking the connection between the output line and the output terminal of the second differential amplifier when the amplification mode setting signal indicates the high speed mode.

5. The amplifying circuit according to claim 1 , further comprising an output switch for connecting the output line to a load, and wherein
the output switch blocks the connection between the output line and the load only during a specified switchover waiting period from a transition point of time at which the amplification mode setting signal shifts from a state indicative of the small offset mode to a state indicative of the high speed mode, or from the state indicative of the high speed mode to the state indicative of the small offset mode.

6. The amplifying circuit according to claim 1 , further comprising a control unit for generating the amplification mode setting signal configured to be switched, at every edge of a clock signal, from a state indicative of the high speed mode to a state indicative of the small offset mode, or from the state indicative of the small offset mode to the state indicative of the high speed mode in an alternate manner.

7. The amplifying circuit according to claim 1 , further comprising a control unit for generating the amplification mode setting signal configured to be switched, at every predetermined period counted by a timer, from a state indicative of the high speed mode to a state indicative of the small offset mode, or from the state indicative of the small offset mode to the state indicative of the high speed mode in an alternate manner.

8. An amplifying circuit for amplifying an input signal applied thereto through its input line and for outputting the amplified signal through its output line, the amplifying circuit comprising:
a first differential pair having a first transistor and a second transistor, the first transistor being configured to pass to a first line a current corresponding to a level of a signal supplied to a gate terminal, the second transistor being configured to pass to a second line a current corresponding to a level of a signal supplied to a gate terminal;
a second differential pair having a third transistor and a fourth transistor, the third transistor having an input capacitance larger than the first transistor and the second transistor and being configured to pass to the first line a current corresponding to a level of a signal supplied to a gate terminal, the fourth transistor having an input capacitance larger than the first transistor and the second transistor and being configured to pass to the second line a current corresponding to a level of a signal supplied to a gate terminal;
a current source for generating a composite current of the current passing through the first line and the current passing through the second line;
an output transistor for sending out to the output line a current corresponding to a voltage of the first line; and
an amplifier switch unit for supplying the input signal to the gate terminal of the first transistor in the first differential pair while connecting the output line to the gate terminal of the second transistor in response to an amplification mode setting signal indicative of a high speed mode, and for supplying the input signal to the gate terminal of the third transistor in the second differential pair while connecting the output line to the gate terminal of the fourth transistor in response to the amplification mode setting signal indicative of a small offset mode.

9. The amplifying circuit according to claim 8 , further comprising a control unit for generating the amplification mode setting signal indicative of the high speed mode only during a period from transition start time at which a level of the input signal starts to increase or decrease until the level of the input signal becomes constant, and for generating the amplification mode setting signal indicative of the small offset mode in other periods.

10. The amplifying circuit according to claim 8 , wherein the amplifier switch unit couples the output line to each of the gate terminals of the third transistor and the fourth transistor in the second differential pair when the amplification mode setting signal indicates the high speed mode.

11. The amplifying circuit according to claim 8 , wherein
the amplifier switch unit includes:
a fifth transistor configured to be turned on so as to connect the input line to the gate terminal of the first transistor when the amplification mode setting signal indicates the high speed mode;
a sixth transistor configured to be turned on so as to connect the output line to the gate terminal of the second transistor when the amplification mode setting signal indicates the high speed mode;
a seventh transistor configured to be turned on so as to connect the output line to the gate terminal of the third transistor when the amplification mode setting signal indicates the high speed mode; and
an eighth transistor configured to be turned on so as

Assignees

• Lapis Semiconductor Co Ltd

Inventors

• Ichikura Hiroyoshi
• Higuchi Koji

Classifications

• H03F3/45475 Primary

  using IC blocks as the active amplifying circuit · CPC title

• H03F2203/45116

  Feedback coupled to the input of the differential amplifier · CPC title

• H03F1/303

  using a switching device (H03F1/305, H03F3/005, H03F3/38 take precedence) · CPC title

• G09G3/36 Primary

  using liquid crystals · CPC title

• H03F2203/45166

  Only one input of the dif amp being used for an input signal · CPC title