Display device and electronic apparatus

US9666129B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9666129-B2
Application numberUS-201615164290-A
CountryUS
Kind codeB2
Filing dateMay 25, 2016
Priority dateJul 2, 2013
Publication dateMay 30, 2017
Grant dateMay 30, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is an active matrix display device using an organic EL panel including: a plurality of pixel circuits each including an organic light emitting diode arranged in a pixel region of the organic EL panel and a plurality of transistors configured to drive the organic light emitting diode; a plurality of scanning lines arranged along a first direction in the organic EL panel; and a plurality of data lines arranged along a second direction that is orthogonal to the first direction. In at least one set of pixel circuits that are adjacent in the first direction, gate electrodes and impurity diffusion regions of the plurality of transistors have an axisymmetric layout. Gate electrodes of at least one set of transistors that are symmetrically arranged in the at least one set of pixel circuits are integrated.

First claim

Opening claim text (preview).

What is claimed is: 1. A light emitting device, comprising: a first data line; a second data line; a light emission control line; a first pixel circuit comprising: a first light emitting element; a first transistor that supplies a first current to the first light emitting element in accordance with a first pixel signal from the first data line; a second transistor connected between the first light emitting element and the first transistor; a second pixel circuit comprising: a second light emitting element; a third transistor that supplies a second current to the second light emitting element in accordance with a second pixel signal from the second data line; a fourth transistor connected between the second light emitting element and the third transistor, wherein the first data line and the second date line extend in a first direction, wherein the second transistor and the fourth transistor have an integrated gate electrode connected to the light emission control line at one connection point, and wherein, in the first direction, the integrated gate electrode forms a mirror image about the connection point. 2. The display device according to claim 1 , wherein the second transistor and the fourth transistor are disposed in linear symmetry for the first direction. 3. The display device according to claim 1 , further comprising: a shielding line arranged between the first data line and the second date line. 4. The display device according to claim 1 , wherein the first transistor and the third transistor are disposed in linear symmetry for the first direction. 5. The display device according to claim 1 , wherein the first data line, the second data line, the light emission control line, the first pixel circuit, and the second pixel circuit are formed on a semiconductor substrate. 6. The display device according to claim 1 , wherein the first light emitting element and second light emitting element are organic light emitting diodes. 7. An electronic apparatus comprising the display device according to claim 1 . 8. An electronic apparatus comprising the display device according to claim 2 . 9. An electronic apparatus comprising the display device according to claim 3 . 10. An electronic apparatus comprising the display device according to claim 4 . 11. An electronic apparatus comprising the display device according to claim 5 . 12. An electronic apparatus comprising the display device according to claim 6 . 13. A light emitting device, comprising: a first data line; a second data line; a light emission control line; a first pixel circuit comprising: a first light emitting element, a first transistor that supplies a first current to the first light emitting element in accordance with a first pixel signal from the first data line; a second transistor connected between the first light emitting element and the first transistor, a second pixel circuit comprising: a second light emitting element; a third transistor that supplies a second current to the second light emitting element in accordance with a second pixel signal from the second data line; a fourth transistor connected between the second light emitting element and the third transistor, wherein the first data line and the second date line extend in a first direction, wherein the second transistor and the fourth transistor have an integrated gate electrode connected to the light emission control line at one connection point, and wherein the connection point is at a center of the integrated gate electrode. 14. An electronic apparatus comprising the display device according to claim 13 .

Assignees

Inventors

Classifications

  • Details of drivers for scan electrodes · CPC title

  • Several active elements per pixel in active matrix panels · CPC title

  • Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

  • with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

  • Precharge or discharge of column electrodes before or after applying exact column voltages · CPC title

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What does patent US9666129B2 cover?
Provided is an active matrix display device using an organic EL panel including: a plurality of pixel circuits each including an organic light emitting diode arranged in a pixel region of the organic EL panel and a plurality of transistors configured to drive the organic light emitting diode; a plurality of scanning lines arranged along a first direction in the organic EL panel; and a plurality…
Who is the assignee on this patent?
Seiko Epson Corp
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 30 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).